VHDL-如何在测试台上创建时钟？ [英] VHDL - How should I create a clock in a testbench?

问题描述

如何在测试台上创建时钟？我已经找到了一个答案，但是堆栈溢出的其他答案表明，有其他方法可以实现这一目标：

How should I create a clock in a testbench? I already have found one answer, however others on stack overflow have suggested that there are alternative or better ways of achieving this:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY test_tb IS 
END test_tb;

ARCHITECTURE behavior OF test_tb IS

    COMPONENT test
        PORT(clk : IN std_logic;)
    END COMPONENT;

   signal clk : std_logic := '0';
   constant clk_period : time := 1 ns;

BEGIN

   uut: test PORT MAP (clk => clk);       

   -- Clock process definitions( clock with 50% duty cycle is generated here.
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;  --for 0.5 ns signal is '0'.
        clk <= '1';
        wait for clk_period/2;  --for next 0.5 ns signal is '1'.
   end process;

END;

（来源此处）

推荐答案

我最喜欢的技术

signal clk : std_logic := '0'; -- make sure you initialise!
...
clk <= not clk after half_period;

我通常用完成信号扩展此值，以允许我停止计时：

I usually extend this with a finished signal to allow me to stop the clock:

clk <= not clk after half_period when finished /= '1' else '0';

---

Gotcha警报：
需要注意如果用另一个常数除以2来计算 half_period ，则模拟器具有时间分辨率设置，通常默认为纳秒...在这种情况下， 5 ns / 2 的结果是 2 ns ，因此您的周期为4ns！将模拟器设置为皮秒，一切都会好起来（除非您需要用皮秒的小数来表示时钟时间！）

---

Gotcha alert: Care needs to be taken if you calculate half_period from another constant by dividing by 2. The simulator has a "time resolution" setting, which often defaults to nanoseconds... In which case, 5 ns / 2 comes out to be 2 ns so you end up with a period of 4ns! Set the simulator to picoseconds and all will be well (until you need fractions of a picosecond to represent your clock time anyway!)

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