从 SystemVerilog 测试台调用 questa sim 命令 [英] call questa sim commands from SystemVerilog test bench

问题描述

我想从我的 SystemVerilog 测试平台调用 questa sim 命令，例如添加波形、添加列表、写入列表

I want to call questa sim commands like add wave ,add list, write list from my SystemVerilog test bench

task add_files_to_list();
add wave -position insertpoint  sim:/top/clk

add list sim:/top/clk 

write list -window .main_pane.list.interior.cs.body /home/simulation/top/example.lst

endtask

但是当我从系统 verilog 执行上述操作时，上述操作不起作用，我必须通过工具手动执行.有没有办法做到这一点.或者我可以从我的系统 verilog 代码中调用 tcl 脚本.

but the above doesn't work when i do from system verilog, i have to do i manually from tool. is there any way to do it. or can i call a tcl script from my system verilog code.

谢谢

推荐答案

 mti_fli::mti_Cmd("command")

见/examples/systemverilog/dpi/cpackages/test.sv

See /examples/systemverilog/dpi/cpackages/test.sv

这篇关于从 SystemVerilog 测试台调用 questa sim 命令的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！