用于Verilog或SystemVerilog的TAP(测试任何协议)模块 [英] TAP (Test Anything Protocol) module for Verilog or SystemVerilog

问题描述

是否有Verilog的TAP(测试任何协议)实现?很好，因为这样我就可以使用证明自动检查我的结果.

Is there a TAP (Test Anything Protocol) implementation for Verilog? It would be nice because then I could use prove to check my results automatically.

更新: 10/9/09:有人问为什么不使用断言. TAP的使用可以为我提供一些不错的报告，例如文件数量和测试数量.它也可以与smolder一起使用，以报告一段时间内的进度.

Update: 10/9/09: It was asked why not use assertions. Partly TAP gives me some good reporting such as number of files and number of tests. It also can be used with smolder for reporting of progress over time.

09年10月12日:我希望在开始和结束时进行最少数量的测试以及ok，diag和fail函数，以尽量减少测试量. is()确实不错，但不是必须的.

10/12/09: I'm looking for a minimal implentation with number of tests at the beginning and end and the ok, diag and fail functions. is() would really nice, but not necessary.

推荐答案

我认为Verilog没有本机TAP实现.我要说的是，使用TAP的全部要点是添加TAP生成器相对简单.如果您打算在Verilog中做很多工作，则可能需要编写自己的文章.

I don't think there is a native TAP implementation for Verilog. I would say that the whole point to using TAP is that adding a TAP generator is relatively straightforward. If you plan to do a lot of work in Verilog, you may want to write your own.

也就是说，您是否看过 veripool ?您可以使用Verilog :: Parser作为生成TAP输出的桥梁，您可以使用 TAP :: Parser & 测试::线束.

That said, have you looked at veripool? You may be able to use Verilog::Parser as a bridge to generate TAP output you could consume with TAP::Parser & Test::Harness.

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