Verilog / SystemVerilog推断出case语句中的闩锁 [英] Verilog/SystemVerilog inferred latch in case statement

问题描述

我在理解为什么我的代码为什么有闩锁时遇到了麻烦

I am having trouble understanding why my code have a latch

logic [1:0] lru_list [0:3];

always_comb begin
    if(reset) begin
        lru_list[0] = 0;
        lru_list[1] = 0;
        lru_list[2] = 0;
        lru_list[3] = 0;
    end
    else begin
        case({access, update, access_index_i < 4})
            3'b101: begin
                lru_list[0] = lru_list[0] + 1;
                lru_list[1] = lru_list[1] + 1;
                lru_list[2] = lru_list[2] + 1;
                lru_list[3] = lru_list[3] + 1;
                lru_list[access_index_i] = 0;
            end
            3'b011: begin
                lru_list[0] = lru_list[0];
                lru_list[1] = lru_list[1];
                lru_list[2] = lru_list[2];
                lru_list[3] = lru_list[3];
                lru_list[access_index_i] = 0;
            end
            default: begin
                lru_list[0] = lru_list[0];
                lru_list[1] = lru_list[1];
                lru_list[2] = lru_list[2];
                lru_list[3] = lru_list[3];
            end
        endcase
    end

end // always_comb

在case语句中，我有一个默认的case，它将捕获所有不匹配的值。我还为数组中的每个索引设置了一个值。我不明白我在哪里将数组隐式设置为隐式值。

In the case statement, I have a default case which will catch all the unmatched values. I have also set each index in the array a value. I don't understand where I am implicitly setting my array a implicit value.

我认为可能与 lru_list [access_index_i] = 0; 有关，但将这两行注释掉仍然会给我保存错误。

I thought it might have to do with lru_list[access_index_i] = 0;, but commenting those two lines out will still give me the save error.

推荐答案

这就是我要开始的内容。

首先添加always语句的敏感度列表。如果在其中，您将有一个重置，所以听起来好像您希望始终使用@（posege clk或posege reset）。我知道您正在使用always_comb，但我很想知道这是否确实消除了问题。

Here is what I would start with.
First add a sensitivity list to the always statement. You have a "reset" if in there so it sounds like you want the always @ (posedge clk or posedge reset). I know you are using always_comb, but I would be curious to know if that actually does remove the issue or not. It would be telling.

编辑：因此，我刚刚意识到您正在使用RHS上的相同变量对LHS变量进行运算。您需要为此计时。否则，当您组合进入计数状态时，它将永远无法解决，因为它始终会无限循环地增加。总是执行@（posege clk或posege reset），您会得到更好的结果。

第二，也许更重要的是，它看起来像您正在使用access_index_i< 4，并尝试从中提取一个位，以组成级联向量的最低有效位{access，update，access_index_i< 4}。如果您向右移动，我认为逻辑会在结果中插入4'b0000，我想这并不是一个开始，所以我想知道在3'b101情况下实际使用了什么位，可以通过{bit，bit，vector}来解决。好像您想说{bit，bit，vector [4]}或类似的东西。您实际上可能正在使用access_index_i的最低3位来寻址您的组合语句。

Second, and probably more important, it looks like you are using access_index_i < 4 and trying to extract a bit from it to make up the least significant bit of your concatenated vector {access, update, access_index_i < 4}. If you are shifting to the right, I think the logic would insert 4'b0000 in the result and I am guessing it is not really a bit to begin with, so I am wondering what bit actually gets used during the 3'b101 case as it would be addressed by {bit,bit,vector}. Seems like you would want to say {bit,bit,vector[4]} or something to that effect. You might actually be using the least significant 3 bits of the your access_index_i to address your combinational statement.

编辑：响应下面的评论。您可以，（这就是我的工作）将问题分为组合部分和计时部分两部分。

reg [3:0] my_sig;
wire [3:0] my_sig_wire;

always @ (posedge clk)
begin
    my_sig <= my_sig_wire;
end

always (*)
   begin
     if(reset)
       begin 
        my_sig_wire = 4'b0000;  // This will also reset the clocked version
       end
     else
        begin
        my_sig_wire = my_sig;  // This is okay, because no matter
                               // how much I alter my_sig_wire, my_sig will
                               // only change on the clock pulse.  So
                               // we avoid the infinite loop problem
        my_sig_wire[index] = 1'b0;  //  Tweak one of the signals for fun.
                                    //  on the next clock, my_sig is updated!
        end
    end

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