如果语句在Verilog中导致闩锁推断? [英] If statements causing latch inference in Verilog?

问题描述

我正在编写用于综合算法的Verilog代码，对于可能导致锁存器推断的情况我有些困惑.下面是代码的这样一个部分，尽管它在模拟中可以正常工作，但我担心它可能会在硬件上引起问题.

I am writing a Verilog code for synthesis of an algorithm, I am a little confused on what cases might cause latches to be inferred. Below is one such section of the code, though it works fine in simulation, I am worried it might cause problems on hardware.

always@(b1 or b2)

.....
// b1_map,b2_map,m1_map & m2_map are derived from combinational functions using b1 & b2
.....

if(b1_map<=20 && m2_map<=20 && b1_map>=0 && m2_map>=0)



begin
accumulator1[b1_map][m2_map]= accumulator1[b1_map][m2_map] + 1;
end

if(b2_map<=20 && m2_map<=20 && b2_map>=0 && m2_map>=0)

begin
accumulator2[b2_map][m2_map]= accumulator2[b2_map][m2_map] + 1;
end

//accumulator1  & accumulator2 are 2d registers mapped like 2d arrays

因此，在这种情况下，我只希望数据在指定限制内​​进行映射.是否会因为未定义其他"方案而推断出闩锁?我没有添加else语句，因为如果数据不在限制范围之内，我就不需要处理任何数据.

So, In this case I want the data to be mapped only if it is in the specified limits. Will a latch be inferred because there is no "else" scenario defined? I didn't add an else statement because there is nothing I want to do with that data if it's not in the limits.

推荐答案

如果正确编写了if语句，就可以了.当通过if语句的路径不更新一个或多个输出时，将生成锁存器.类似于以下代码的代码将生成一个闩锁:

If you write your if statements correctly, you will be fine. Latches are generated when there are paths through the if statement that do not update one or more of the outputs. Code like the following will generate a latch:

always @* begin
    if (a) begin
        b <= c & d;
        e <= f;
    end else begin
        b <= c | d;
    end
end

是否仅在a为真时才分配e?这需要一个锁存器才能正确实现.

Notice that e is assigned only when a is true? This requires a latch to implement correctly.

另一个可能会产生闩锁的可能性是，当灵敏度列表中不包含代码中使用的信号时.

Another posibility that will generate a latch is when the sensitivity list does not contain a signal used in the code.

always @(a) begin
    if (a) begin
        b <= c & d;
    end else begin
        b <= c | d;
    end
end

此代码将在c和d或b上生成锁存器，因为它仅允许在a更改时更新b.

This code will generate latches on c and d or on b because it will only allow b to be updated when a changes.

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