如何使用VHDL实现时钟倍频 [英] How to implement clock frequency multiplier using VHDL

问题描述

我是VHDL编码的初学者.我正在尝试使用VHDL实现倍频.我已经实现了分频器，但是倍频器并不是那么容易.请给出实现该想法的方法.

I am a beginner in VHDL coding. I am trying to implement frequency multiplier using VHDL. I have implemented frequency divider, but frequency multiplier is not that easy. Please give an idea for implementing that.

推荐答案

要在FPGA中实现，您必须使用专用的FPGA资源，例如 Altera 和 Xilinx )或数字时钟管理器(DCM)(请参见

For implementation in a FPGA, you must use a dedicated FPGA resource like Phase-Locked Loop (PLL) (see Altera and Xilinx) or Digital Clock Managers (DCM) (see Xilinx) to multiply a frequency.

这些资源可以基于输入频率来创建输出频率，例如:

These resources can create an output frequency based on an input frequency like:

f_out = (N / M) * f_in

PLL和DCM资源是特定于设备的，通常是非常高级的资源，可以对相位，延迟等进行额外控制，因此请查看所使用设备中的资源.

The PLL and DCM resources are device specific, and often very advanced resources, that allows additional control over phase, delay, etc., so take a look at the resources in the device you are using.

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