VHDL门控时钟如何避免 [英] VHDL Gated Clock how to avoid
问题描述
我收到了避免门控时钟的建议，因为这可能会导致松弛和计时成本问题。但是我想问一下，我可以像门控时钟那样考虑什么。
例如：
此代码具有门控时钟，因为StopCount对其进行了控制。
process（ModuleCLK）如果（rising_edge（ModuleCLK）和StopCount ='0'）则
开始
如果ModuleEN ='0'则
然后
RESET < ; ='0';
POWER< =‘1';
EN< =‘0’;
CLOCK< = 0;
SERIAL< =‘0’;
elsif
此代码还控制了时钟？
进程（ModuleCLK）
如果ModuleEN ='0'开始
，则
RESET< ='0';
POWER< =‘1';
EN< =‘0’;
CLOCK< = 0;
SERIAL< =‘0’;
elsif（rising_edge（ModuleCLK））然后
门控时钟一词在ASIC技术中经常用于仅在满足条件（1）时才生成时钟脉冲的时钟，因此门控时钟是时钟源的属性。可以使用锁存器和AND门制作门控时钟，如下图所示，这种设计需要特别注意以解决您提到的时序问题，因此不适合FPGA设计：
您显示的代码使用触发器上的启用来更新触发器值，具体取决于启用，因此这是时钟启用，而不是门控时钟。
第一个代码可以并且应该被写为：
进程（ModuleCLK）是
begin
（如果rising_edge（ModuleCLK），则
，如果StopCount ='0'，则
...-如果StopCount ='0'，则在时钟更新
这反映了通常在FPGA中实现设计的方式，在该FPGA中，触发器始终被计时（ ModuleCLK ），但仅在条件（ StopCount ='0'）为真时更新输出。
第二个代码示例看起来像异步重置，只是该代码在敏感度列表中应该具有重置条件（ ModuleEN ）（问题中未填写）码）。由于触发器不需要时钟时钟来更改值，因此会发生异步复位。唯一的要求是重置条件为true，然后值的更改将与任何时钟异步发生。
这样一种在VHDL中正确编写触发器的方法是，输入 a 并输出 z ，就像：
进程（重置，时钟）是
如果重置='1'，则开始
，然后
z< ='0';
elsif上升边缘（时钟），然后
（如果enable =‘1，则
z <= a;
结尾，如果；
结尾，如果；
结束程序；
在Altera Quartus II中，这会创建RTL数字，例如：
然后在Arria II设备中实现以下操作：
这表明触发器实际上是在时钟的每个上升沿更新的，因此时钟使能通过组合设计（LUT）实现，当enable为false（0）时将当前数据反馈到触发器，或者当enable为true（1）时从 a 给出新数据。
I've received an advice to avoid gated clock because it may cause problems with slacks and timing costraints. But I want to ask what I can consider like a gated clock. For example:
This code have gated clock because StopCount gate it.
process(ModuleCLK)
begin
if (rising_edge(ModuleCLK) and StopCount = '0') then
if ModuleEN = '0' then
RESET <= '0';
POWER <= '1';
EN <= '0';
CLOCK <= '0';
SERIAL <= '0';
elsif
This code have also gated clock?
process(ModuleCLK)
begin
if ModuleEN = '0' then
RESET <= '0';
POWER <= '1';
EN <= '0';
CLOCK <= '0';
SERIAL <= '0';
elsif (rising_edge(ModuleCLK)) then
The term "gated clock" is often used in ASIC technology for a clock where the clock pulse is only generated when a condition is true (1), so the gated clock is a property of the clock source. A gated clock can be made with a latch and AND gate, like show below, and that kind of design requires special attention to address the timing issues you mention, thus is not suited for FPGA design:
The code you have shown uses an enable on the flip-flop to update the flip-flop value depending on the enable, so this is a clock enable, not a gated clock.
The first code can, and should, be written as:
process (ModuleCLK) is
begin
if rising_edge(ModuleCLK) then
if StopCount = '0' then
... -- Update at clock if StopCount = '0'
This reflect how the design is typically implemented in a FPGA, where the flip-flop is always clocked (ModuleCLK) but where the output is only updated if the condition (StopCount = '0') is true.
The second code example looks like asynchronous reset, except that the code should have reset condition (ModuleEN) in the sensitivity list (missing in the question code). The asynchronous reset occurs since no clock clock is required for the flip-flops to change value; the only requirement is that the reset condition is true, and then a change of value occurs asynchronously to any clock.
So a way to properly write flip-flops in VHDL, with input a and output z, is like:
process (reset, clock) is
begin
if reset = '1' then
z <= '0';
elsif rising_edge(clock) then
if enable = '1' then
z <= a;
end if;
end if;
end process;
In Altera Quartus II this creates RTL figure like:
The implementation in an Arria II device is then:
This shows that the flip-flop up actually updated at every rising edge of the clock, so the clock enable is implemented through a combinatorial design (LUT), where the current data is feed back to the flip-flop when enable is false (0), or new data is given from a when enable is true (1).
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