在 VHDL Modelsim 中调试迭代限制错误 [英] Debugging Iteration Limit error in VHDL Modelsim

问题描述

我正在为 Modelsim 上的 d 触发器编写 VHDL 代码，但在尝试模拟时出现错误:

I'm writing VHDL code for a d-flip-flop on Modelsim and I get an error when I try to simulate it:

错误:(vsim-3601) 在 400 ps 时达到迭代限制.

Error: (vsim-3601) Iteration limit reached at time 400 ps.

我不确定这意味着什么，但我已经查看了我的大部分源代码以查找错误，但没有成功.谁能猜出可能是什么问题?

I'm not sure what it means, but I've looked through much of my source code for errors to no success. Can anyone guess what the problem might be?

推荐答案

此错误通常表示 ModelSim 陷入无限循环.在 VHDL 中，当一个信号被放置在敏感列表中并且这个信号在这个过程中被改变时，就会发生这种情况.信号改变，触发过程，信号改变，信号再次触发过程，循环继续.

This error usually indicates that ModelSim is stuck in an infinite loop. In VHDL, this can happen when a signal is placed in the sensitivity list and this signal is changed in the process. The signal changes, triggering the process, which changes the signal, which again triggers the process and the cycle continues.

以下是一个导致无限循环的过程的简单示例:

The following is a simple example of a process that causes an infinite loop:

PROCESS (count)

BEGIN

count <= not count;

END PROCESS;

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