Verilog中信号边缘检测的正确方法 [英] Proper way for signal edge detection in Verilog

问题描述

我想检测信号的上升沿从触发器AA到BB

                    +----+
  A ----------------|    |----- OUT
        +----+      | BB |
  B ----|    |------|>   |
        | AA |      +----+
clk ----|>   |
        +----+

Verilog 代码:

Verilog code:

    module edge_detect (
        input A,
        input B,
        input clk,
        output OUT
    );

        reg AA;
        reg BB;

        always @(posedge clk) begin
            AA <= B;
        end

        always @(posedge AA)begin
            BB <= A;
        end

        assign OUT = BB;
    endmodule

AA 的输出用作 BB 的时钟，表示 AA 已完成其工作，然后 BB现在可以继续其操作.

The output of AA is used as a clock to BB saying that AA has done its job and then BB can now continue its operation.

我很少看到这个代码.这是一个好习惯吗?

I rarely see this code. Is this a good practice?

如果没有，是否还有其他适当的方法来检测信号的边缘?

If not, are there any other proper way to detect an edge of a signal?

推荐答案

由于各种原因，人们往往不喜欢将数据用作时钟.

People tend to frown on using data as clocks for various reason.

就我个人而言，如果我正在写这篇文章，我会选择:

Personally if I was writing this I'd go with:

module edge_detect (
    input A,
    input B,
    input clk,
    output OUT
);

    reg AA;
    reg BB;
    wire enA;

    always @(posedge clk) begin
        BB <= B;
    end

    assign enA = !BB && B;

    always @(posedge clk)begin
       if (enA) begin
            AA <= A;
      end
    end

    assign OUT = AA;
endmodule

                                +----+
  A ----------------------------|D   |----- OUT
                     +---+      | AA |
      /--------------|   |      |    |
      | +----+       |AND|------|E   |
  B ----|    |------o|   |      |    |
        | BB |       +---+      |    |
clk ----|>   |          clk ----|>   |
        +----+                  +----+

不过行为有点不同.

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