如何在verilog中获得粗略的随机信号不好? [英] how to get the a coarse random signal in the verilog not fine?

问题描述

现在，我试图使粗略的随机信号不好.所以我在 verilog 中使用了 $urandom 命令.但我仍然无法获得粗略的随机信号.

Now, I'm trying to make a coarse random signal not fine. So I'm using the $urandom command in the verilog. But still I can't get the coarse random signal.

以下是我的随机 verilog 代码，但我不知道如何获得不好的粗随机信号.

the below is the my random verilog code but I don't know how to get the a coarse random signal not fine.

always@(clk) begin

temp = $urandom;

end

编辑

粗随机信号意味着我可以用加法器信号告诉你.

EDIT

coarse random signal means I can tell you by using adder signal.

reg [29:0] temp;

always@(posedge clk or negedge rst) begin
if(!rst)
temp <= 0;
else
temp <= temp + 1;
end

从这里，我们可以看到 temp[0] 和 temp[29] 信号的差异，我的意思是粗随机信号有足够的变化周期，但发现随机信号意味着 temp[0] 是快速变化的信号.

From here, we can see temp[0] and temp[29] signals differences what i mean the coarse random signal have a change with enough change period but find random signal means like temp[0] is rapidly changed signal .

推荐答案

好吧，我能想到两种做法，都需要使用之前的temp状态.

OK, I can think of two ways of doing, both requires using the previous state of temp.

randomize(temp) with {foreach (temp[bitt]) temp[bitt] ^ const'(temp[bitt]) dist {1:=1, 0:=10};};

上面说对于 temp 的每一位，随机位与其当前状态相同的概率是不同的 10 倍.

The above says for each bit of temp, the probability of a random bit being the same its current state is 10 times more likely than being different.

  randomize(temp) with {$countones(temp^const'(temp)) < 10;};

上面说可以与当前值不同的总位数小于十.

The above says the total number of bits that can be different from the current value is less that ten.

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