Verilog 中的有符号乘法溢出检测 [英] Signed multiplication overflow detection in Verilog

问题描述

这里是初学者.我正在尝试在 Verilog 中编写一个简单的 16 位微处理器并在 Spartan 6 上实现它. ALU 实现所有有符号操作(根本没有无符号操作).所有输入都是连线并带有符号.结果存储在签名寄存器中.

Beginner here. I'm trying to code a simple 16-bit microprocessor in Verilog and implement it on a Spartan 6. The ALU implements all signed operations (no unsigned operations at all). All inputs are wires and are signed. The result is stored in a signed register.

我的问题是找到一种合理的方法来检测溢出.当前检测溢出的速度并不重要，因为它所做的只是触发故障并停止系统.

My problem is finding a sensible way to detect overflow. It doesn't currently matter how quickly the overflow is detected, since all it does is trigger a fault and halt the system.

我相信我已经找到了如何检测加法和减法溢出的方法，但我还是希望得到保证.

I believe I've figured out how I could detect overflow in addition and subtraction, but I'd like assurance anyway.

这里的补充，其中 o 是溢出标志寄存器:

Here's addition, where o is the overflow flag register:

if((a_in >= 0) && (b_in >= 0) && (res_out < 0)) o <= 1'b1;
else if((a_in < 0) && (b_in < 0) && (res_out >= 0)) o <= 1'b1;
else o <= 1'b0;

这里是减法:

if((a_in >= 0) && (b_in < 0) && (res_out < 0)) o <= 1'b1;
else if((a_in < 0) && (b_in > 0) && (res_out >= 0)) o <= 1'b1;
else o <= 1'b0;

控制矩阵负责 a_in 和 b_in 的保持时间，以便完成溢出检测，因为它仅在计算结果后(即下一个时钟周期)完成.

The control matrix takes care of the hold times for a_in and b_in so that the overflow detection could complete, as it's only done once the result has been calculated (on the next clock cycle that is).

我在这里环顾四周，发现的只是检测其他语言(例如 C 或 C++)中的溢出.我正在寻找有符号乘法检测溢出的示例实现.

I did some looking around here and all I've found is detecting overflow in other languages such as C or C++. I'm looking for an example implementation for detection overflow in signed multiplication.

输入 a_in 和 b_in 都是有符号线并且都是 16 位宽.结果寄存器 res_out 是有符号的，也是 16 位宽.理想情况下，我有一个 33 位宽的结果寄存器，无论如何都不会发生溢出，但这不是一个选项.

Both inputs a_in and b_in are signed wires and are 16 bits wide. The result register res_out is signed, also 16 bits wide. Ideally, I'd have a 33 bit wide result register, in which overflow cannot occur anyway, but this is not an option.

感谢帮助.也欢迎任何更好的方法来检测加法和减法溢出.

Help is appreciated. Any better ways to detect overflow in addition and subtraction are also welcome.

推荐答案

另外看检测溢出和下溢，分析一个简单的4位例子，符号扩展到5位.

Looking at detecting Overflow and underflow in addition, Analysing a simple 4 bit example, sign extended to 5 bits.

添加所有+ve

  3 : [0]0011
+ 3 : [0]0011
= 6 : [0]0110

带负数

  -3 : [1]1101 
+ -3 : [1]1101
= -6 : [1]1010

现在导致溢出:结果应该是+8，但不能用4位表示.

Now causing an overflow : Result should be +8 but can not represent that in 4 bits.

  +7 : [0]0111
  +1 : [0]0001 
  +8 : [0]1000

现在导致下溢:结果应该是-9，但不能用4位表示.

Now cause underflow : Result should be -9 but can not represent that in 4 bits.

  -8 : [1]1000
+ -1 : [1]1111
  -9 : [1]0111 

因此，如果我们将输入符号扩展 1 位，很容易检测上溢和下溢

Therefore overflow and underflow are easy to detect if we sign extend the inputs by 1 bit

localparam WIDTH = 4;
localparam MSB   = WIDTH-1;
logic [WIDTH-1:0] a;
logic [WIDTH-1:0] b;
logic [WIDTH-1:0] result;
logic extra;
logic overflow;
logic underflow;


always @* begin
  {extra, result} = {a[MSB], a} + {b[MSB], b} ;
  overflow  = ({extra, result[MSB]} == 2’b01 );
  underflow = ({extra, result[MSB]} == 2’b10 );
end

关于乘法我不明白为什么你不能有一个 32 位寄存器.即使您将最终输出减少到 16.

Regarding multiplication I do not understand why you can not have a 32 bit register. even if you reduce the final output to 16.

在执行位缩减时，您需要检查该值是否低于最大值并高于缩减宽度可以支持的最小负数.

When performing the bit reduction you would need to check that the value is under the max and above the minimum negative number that you can support with the reduced width.

注意:此外，结果比最大输入大 1 位.截断回原始宽度时发生上溢/下溢.

NB: In addition the result grows 1 bit bigger than largest input. The overflow/underflow occurs when truncating back to original width.

乘法的结果是两者的宽度相加，16bits * 16bits 结果为 32 位答案.很确定你不需要 33 位.如果您不保持全宽，则很难判断结果在截断时是否会溢出.将这些东西设计为具有广泛的组合结果并且只通过触发器输出这么多位以供 ALU 的最终输出是很常见的.

With multiplication the result is the width of both added together, 16bits * 16bits results in a 32 bit answer. Pretty sure you do not need 33 bits. If you do not keep the full width then it is pretty hard to tell if the result will overflow when truncated. It is quite common to design these things with a wide combinatorial result and only output so many bits through a flip-flop for the final output from the ALU.

我认为保持 32 位输出并将其与有符号的 16 位数字的最大值/最小值进行比较，将比仅使用 16 位乘法器和额外的逻辑来检测溢出条件合成得更小.

I think that keeping a 32 bit output and comparing it to the max/min of a signed 16 bit number, will synthesise smaller than only using 16 bit multiplier and extra logic to detect the overflow condition.

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