Verilog - 浮点乘法 [英] Verilog - Floating points multiplication
问题描述
我们在使用 Verilog 时遇到了问题.我们必须使用两个浮点(二进制)的乘法，但它不能 100% 完美地工作.
We have a problem with Verilog. We have to use multiplication with two floating points(binary), but it doesn't work 100% perfectly.
我们有一个请求 m[31:0].第一个数字(逗号前)是 m[31:16] 和逗号后的数字 m[15:0] 所以我们有:
We have a Req m[31:0]. The first numbers (before the comma) are m[31:16] and the numbers after comma m[15:0] so we have like:
m[31:16] = 1000000000000000；m[15:0] = 1000000000000000;
m[31:16] = 1000000000000000; m[15:0] = 1000000000000000;
m[31:0] = 10000000000000000(.)1000000000000000;
m[31:0] = 10000000000000000(.)1000000000000000;
问题是:我们想乘以带小数位的数字，但我们不知道如何做.例如:m = 2.5 二进制.m*m 的结果是 6.25.
The Problem is: we want to multiplicate numbers with decimal places, but we don't know how. For example: m = 2.5 in binary. The result of m*m is 6.25.
推荐答案
该问题并未完全涵盖对定点数的理解，因此将涵盖一些可能与 OP 无关的背景知识.
The question does not fully cover what is understood about fixed-point numbers, therefore will cover a little background which might not be relevant to the OP.
无符号二进制(基数为 2)数字的十进制加权，示例为 4 位遵循以下规则:
The decimal weighting of unsigned binary (base 2) numbers, 4bit for the example follows this rule:
2^3 2^2 2^1 2^0 (Base 2)
8 4 2 1
仅供参考，权力保持不变，基础已更改.对于 4 十六进制，它将是:
Just for reference the powers stay the same and the base is changed. For 4 hex it would be:
16^3 16^2 16^1 16^0
4096 256 16 1
回到基数 2，对于有符号的二进制补码数，MSB(最高位)变为负数.
Back to base 2, for twos complement signed number the MSB (Most Significant Bit) becomes negative.
-2^3 2^2 2^1 2^0 (Base 2, Twos complement)
-8 4 2 1
当我们插入一个二进制小数点或小数位时，模式会继续.4 个整数位 4 个小数位.
When we insert a binary point or fractional bit the pattern continues. 4 Integer bits 4 fractional bits.
Base 2: Twos complement 4 integer, 4 bit frational
-2^3 2^2 2^1 2^0 . 2^-1 2^-2 2^-3 2^-4
-8 4 2 1 . 0.5 0.25 0.125 0.0625
不幸的是，Verilog 没有定点格式，因此用户必须跟踪二进制小数点并使用缩放数字.小数点 . 不能用于存储为 reg 或 logic 的 verilog 数字中，因为它们本质上是整数格式.然而，verilog 在放在数字声明中时确实会忽略 _，因此它可以用作数字中的二进制小数点.它的使用只是象征性的，对语言没有意义.
Unfortunately Verilog does not have a fixed-point format so the user has to keep track of the binary point and worked with scaled numbers. Decimal points . can not be used in in verilog numbers stored as reg or logic as they are essentially integer formats. However verilog does ignore _ when placed in number declarations, so it can be used as the binary point in numbers. Its use is only symbolic and has no meaning to the language.
在上述格式中，2.5 将由 8'b0010_1000 表示，问题有 16 个小数位，因此您需要在 _ 后放置 16 位以保持二进制指向正确的位置.
In the above format 2.5 would be represented by 8'b0010_1000, the question has 16 fractional bits therefore you need to place 16 bits after the _ to keep the binary point in the correct place.
如果我们有两个数字 A 和 B，结果 A*B 的宽度将是:
If we have two numbers A and B the width of the result A*B will be:
Integer bits = A.integer_bits + B.integer_bits.
Fractional bits = A.fractional_bits + B.fractional_bits.
因此 [4 Int, 4 Frac] * [4 Int, 4 Frac] => [8 Int, 8 Frac]
Therefore [4 Int, 4 Frac] * [4 Int, 4 Frac] => [8 Int, 8 Frac]
reg [7:0] a = 0010_1000;
reg [7:0] b = 0010_1000;
reg [15:0] sum;
always @* begin
sum = a * b ;
$displayb(sum); //Binary
$display(sum); //Decimal
end
// sum == 00000110_01000000; //Decimal->6.25
EDA Playground 的示例.
由此您应该能够更改深度以适应任何类型的定点数.可以通过部分选择正确的位来转换回 16 Int 16 小数.如果您需要饱和而不是溢出，请小心.
From this you should be able to change the depths to suit any type of fixed point number. and cast ing back to a 16 Int 16 fractional number can be done by part selecting the correct bits. Be careful if you need to saturate instead of overflowing.
有一个相关的问答，它有 22 个小数位.
There is a related Q&A that has 22 fractional bits.
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