乘法，乘法寄存器verilog [英] Multiplication, multiply register verilog

问题描述

有没有办法将一个寄存器/导线与一个值相乘?

is there a way to multiply a register/ wire with a value?

例如

... input wire [13:0] setpoint ...
 if (timer>(setpoint*0.95)) 

推荐答案

是可以的，但是乘数可能很大，因此请谨慎使用.在这种情况下，被乘数是固定的，因此会大大降低逻辑.

Yes this is possible, but multipliers can be quite large so use with caution. In this case the multiplicand is fixed so it will reduce the logic down quite a lot.

在RTL中，实数(如0.95)没有太大的意义，您需要乘以不动点数，这也将限制可以表示0.95的精度.

In RTL a real (as in 0.95) does not have much meaning you need to multiply by a fixed point number, which will also limit the precision which you can represent 0.95.

允许10个二进制位，缩放比例为2 ^ 10. 0.1111001100 => 0.94921875.为了进行比较，您需要跟踪乘法结果如何增长.

Allowing 10 binary places, a scaling of 2^10. 0.1111001100 => 0.94921875. For the comparison you need to keep track of how the result of the multiply grows.

a_int_bits.a_frac_bits * b_int_bits.b_frac_bits =
  (a_int_bits + b_int_bits) . (a_frac_bits + b_frac_bits)

因此，对于要添加到0.95表示中的小数位，比较中的timer将需要LSB填充.

Therefore the timer in the comparison would need to be LSB padded for the fractional bits that are added to the representation of 0.95.

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