用 Verilog 写寄存器路径哪种方式更好 [英] Which way is better writing a register path in Verilog

问题描述

解决方案 1

reg q;
always @(posedge clk or negedge rst_n)
if (!rst_n)
  q <= 1'b0;
else
  if (en_a)
    q <= da;
  else if (en_b)
    q <= db;
  else if (en_c)
    q <= dc;

解决方案 2

reg qw, qr;
always @(*)
if (en_a)
  qw = da;
else if (en_b)
  qw = db;
else if (en_c)
  qw = dc;

always @(posedge clk or negedge rst_n)
if (!rst_n)
  qr <= 1'b0;
else
  qr <= qw;

我经常使用解决方案1，我可以在许多其他工程师的代码中找到它.Solution 2 分离了组合逻辑部分和序列逻辑部分，经典的FSM风格.

I use solution 1 a lot and I can find it a lot in many other engineers' code. Solution 2 seperates the combinational logic part and sequencial logic part, the classic FSM style.

我的问题是，(对于solution 2)是否比solution 1 有实际优势?两种解决方案有什么区别?

My question is, (for solution 2)is there an actual advantage over solution 1? And what is the difference between two solutions?

推荐答案

部分取决于设计和合成器的大小.对于大型 FSM 设计，两个总是块的方法使用更少的面积，通常具有更好的时序和更少的代码行，而不是等效的始终块方法.来自 Cliff Cummings 的 这篇论文详细介绍了一个、两个、三个总是阻止方法.他在一些旧论文这里和此处.几年过去了，我的团队将这些样式与我们自己的代码和工具进行了比较；我们可以得出与 Cliff 相同的结论.你应该尝试自己比较.

It partly depends on the size of the design and the synthesizer. For large FSM designs a two always block approach uses less area, often has better timing, and fewer lines of code then its equivalent one always block. This paper from Cliff Cummings goes into detail on the differences between the one, two, three always block approaches. He been recommending this style for a while in some older papers here and here. Several years a go my team compared the styles with our own code and tools; we can came to the same conclusion as Cliff. You should try comparing on your own.

始终阻止的两个优点是:

The two always block advantages are:

• 在波形或显示语句中查看时钟之前的触发器的下一个值.使用 always 块，您需要计算值.
• 不会意外地创建一个意外的触发器
  • 注意:存在推断意外锁存器的风险，但是由于设计中很少有预期的锁存器，因此很容易在 linting 和综合工具的报告中发现它们.意外的触发器更难发现.
  • 几行代码
  • 面积较小
  • 更好的时机

  始终阻止的优点是:

  • 通常，一个always块比两个always块稍微模拟效率更高 - (悬崖 SNUG1998SJ FSM，第 10 页)
  • 不会意外地推断出意外的闩锁
  • 当严格遵循 IEEE1364-1995 时:
    • @(*) 是在 IEEE1364-2001 中添加的.在IEEE1364-1995中，组合always块中使用的每个信号外部驱动信号都需要列在敏感列表中.
      • 示例:@(en_a or en_b or en_c or da or db or dc or qr)
      • Generally one always block is slightly more simulation-efficient than the two always block - (Cliff SNUG1998SJ FSM, page 10)
      • Will not accidentally infer an unintended latch
      • When strictly following IEEE1364-1995:
        • @(*) was added in IEEE1364-2001. In IEEE1364-1995, every signal external driving signal used in the combinational always block needed to be listed in the sensitively list.
          • Example: @(en_a or en_b or en_c or da or db or dc or qr)
          • 只看一个街区

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