Verilog:添加寄存器的单个位(组合逻辑，寄存器宽度可参数化) [英] Verilog: Adding individual bits of a register (combinational logic, register width is parameterizable)

问题描述

我试图想出一种方法来添加寄存器的各个位.例如，if regA = 111000 then regB = 3(regA 的位总和).1) Verilog 或 SystemVerilog 中是否有任何可合成的函数/运算符可以直接用于执行此操作?

I am trying to come up with a way to add individual bits of a register. eg, if regA = 111000 then regB = 3 (Sum of bits of regA). 1) Is there any synthesizable function/operator in Verilog or SystemVerilog which I can directly use to do this operation?

如果不是，那么问题可能有点有趣，特别是因为操作必须在一个时钟周期内完成(纯组合逻辑)并且寄存器宽度是可参数化的.

If not, then maybe the problem is a little interesting, especially because the operation has to be done in one clock cycle (pure combinational logic) and the register width is parameterizable.

2) 如果没有内置的 Verilog 或 SystemVerilog 运算符，那该怎么办?

2) In case there is no inbuilt Verilog or SystemVerilog operator then what can be done?

谢谢，乌杰瓦尔

推荐答案

Verilog(IEEE Std 1364-2001 或更新版本):

Verilog (IEEE Std 1364-2001 or newer):

integer i;
always @* begin
  B = WIDTH_LOG2'b0;
  for (i=0; i<WIDTH; i=i+1)
    B = B + A[i];
end

SystemVerilog(IEEE Std 1800-2005 或更新版本):

SystemVerilog (IEEE Std 1800-2005 or newer):

always_comb begin
  B = '0; // fill 0
  foreach(A[i])
    B += A[i];
end

两者都会合成为组合逻辑.没有锁存器或触发器.

Both will synthesize to combination logic. No latches or flops.

SystemVerilog 确实有 $countones()，但我不确定它是否可合成.如果是这样:always_comb B = $countones(A)

SystemVerilog does have $countones(), but I'm unsure if it is synthesizable. Ff it is then: always_comb B = $countones(A)

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