VHDL 中数组的硬件表示 [英] Hardware representation for arrays in VHDL

问题描述

使用 VHDL，我希望有一些寄存器可以在每个寄存器中存储 16 位.所以我发现 VHDL 有一个内置数组，我想用它在 iy 的每个元素中存储 16 位，所以我想知道 VHDL 是否将此数组映射到实际寄存器?

解决方案

简短的回答是否定的 - 数组类型不映射到寄存器.

长答案:

VHDL 中的数组类型只是相同类型元素的索引集合.就您而言，您可能会使用数组作为寄存器组的输出.

因此，假设您有一组 8 个寄存器，每个寄存器保存 16 位.该组的输出将是一个 16 位向量数组(大小为 8).该寄存器组的组件声明如下所示:

<前>组件 reg8x16港口(时钟:在 std_logic 中；重置:在 std_logic 中；启用:在 std_logic 中；rout : out r_array(0 到 7));终端组件；

rout 是来自寄存器组的已注册输出数组.因此，您可以使用 rout(0) 取消引用 bank 中寄存器 0 的输出，其类型为 std_logic_vector(15 downto 0).

另外，不要忘记在某处(通常在包文件中)声明数组类型.它看起来像:

type r_array 是 std_logic_vector(15 downto 0) 的数组(整数范围<>)；

(integer range <>) 语句是数组索引范围的一种占位符 - 它会在稍后使用数组类型时填充(例如在我们的组件声明中)以上).

我不确定这是否能回答您的问题.我不会详细介绍如何创建 reg8x16 组件.基本上，您只需创建一个 16 位寄存器，其输出类型为 std_logic_vector(15 downto 0);(您可以在线查找如何执行此操作...这是非常基本的 VHDL).然后您只需实例化其中的 8 个寄存器，并将它们放入名为 reg8x16 的组件中.

Using VHDL i want to have a some registers that store 16 bit in each one. So i found that VHDL have a built in array,and i want to use it to store 16 bit in each element in iy so i want to know if VHDL map this array to actual registers or not?

解决方案

The short answer is no - the array type does not map to a register.

The long answer:

The array type in VHDL is just an indexed collection of elements of the same type. In your case, you'd probably use an array as the output from a register bank.

So, say you have a bank of 8 registers each holding 16 bits. The output from this bank would be an array (of size 8) of 16-bit vectors. The component declaration for this register bank would look something like this:

 component reg8x16
  port(
   clock: in std_logic;
   reset: in std_logic;
   enable: in std_logic;
   rout : out r_array(0 to 7)
   );
 end component; 

rout is your array of registered outputs from the register bank. So you can dereference the output of register 0 from the bank using rout(0), which is of type std_logic_vector(15 downto 0).

Also, don't forget to declare the array type somewhere (usually in a package file). It would look something like:

type r_array is array (integer range <>) of std_logic_vector(15 downto 0);

The (integer range <>) statement is a kind of placeholder for the array index range - it will be filled in later when the array type is used (such as in our component declaration above).

I'm not sure if this answers your question or not. I won't go into the specifics of how to create the reg8x16 component. Basically, you just create a 16-bit register whose output is of type std_logic_vector(15 downto 0); (you can look up how to do this online...it's pretty basic VHDL). Then you just instantiate 8 of those registers, and put them in the component named reg8x16.

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