需要帮助读取内存数组的内容并在 vhdl 中获取计数 [英] Need help in Reading contents of memory array and get a count in vhdl

问题描述

输入数组:Ram = {D D D D D 3 3 3 3 7 7 7 9 9 8 8};
我期待输出如下:

input array: Ram = {D D D D D 3 3 3 3 7 7 7 9 9 8 8};
I am expecting the output as below:

计数 = {0 0 0 4 0 0 0 3 2 2 0 0 0 5 0 0};

Count = {0 0 0 4 0 0 0 3 2 2 0 0 0 5 0 0};

即计算出现的次数，例如有五个 D、四个 3、三个 7、两个 9 和两个 8，因此 Count 数组在第 D 个索引中有 5 个，在第 3 个索引中有 4 个，在第 7 个索引中有 3 个等等

That is to count the number of occurances, like there are five D's , four 3's , three 7's, two 9's and two 8's so that Count array has 5 in Dth index, 4 in 3rd index, 3 in 7th index and so on.

我的代码如下:

 architecture behav of Bitcount is
   signal cnt: count_type := (others=> (others=>'0'));
   use ieee.numeric_std.all;

  begin 
  Countproc:process(clk) 
  begin
   if (clk'event and clk='1' ) then
    if Enable='1' then
       if (Read_bit='1') then
           for k in 0 to 15 loop
              for i in 0 to 15 loop
                if ( Ram(k) = std_logic_vector(to_unsigned(i, 4)) )then         
                  cnt(i) <= cnt(i) + "01";
                end if;
              end loop;
        end loop;
      end if;
   end if;
   Count <= cnt;
  end if;
end process Countproc;
end behav;

但它不符合我的预期.请帮忙

but its not working as my expectation . pls help

推荐答案

你的问题是 cnt 是一个 信号.它必须是一个变量.

Your problem is that cnt is a signal. It needs to be a variable.

进程中的代码行顺序执行.每当执行包含信号赋值(<=)的一行代码时，都会将一个事件放入事件队列以驱动目标信号(cnt 在这种情况下)在下一个增量周期(假设目标信号因此发生了一些变化).事件队列是模拟器的待办事项"列表；增量周期是模拟器的一次迭代；一旦当前迭代中正在执行的所有进程都暂停，将进行下一次迭代.

The lines of code within a process are executed sequentially. Whenever a line of code containing a signal assignment (<=) is executed, an event is put on the event queue to drive the target signal (cnt in this case) on the next delta cycle (assuming there is some change to the target signal as a result). The event queue is the simulator's "to do" list; a delta cycle is one iteration of the simulator; the next iteration will occur once all the processes that are executing in the current iteration suspend.

如果在进程的任何执行过程中遇到另一个分配给同一目标信号的信号，则(通常*)事件队列中与该信号相关的任何其他事件都将被删除.因此，在您的示例中，每次遇到此行时(将是 16*16=256 次):

If, during any execution of a process, another signal assignment to the same target signal is encountered, then (usually*) any other events on the event queue relating to that signal are deleted. So, in your example, every time this line is encountered (which it will be 16*16=256 times):

cnt(i) <= cnt(i) + "01";

不是增加 cnt(i)(这是我假设您期望发生的)，而是删除和替换与 cnt(i) 相关的所有先前事件用一个新的事件来驱动 cnt(i) 用 它在进程开始执行之前的值加一.信号 cnt(i) 在进程完成执行(以及所有其他进程)之前不会获得其新值.

Instead of incrementing cnt(i) (which is what I assume you are expecting to happen), all previous events relating to cnt(i) are deleted and replaced with a new event to drive cnt(i) with the value it had before the process started executing plus one. The signal cnt(i) does not get its new value until the process completes executed (and all other processes too).

变量不会表现出这种行为；变量的行为就像变量在任何软件语言中的行为一样.当一行代码遇到变量赋值 (:=) 时，变量会立即更新，因此其值可立即用于进一步计算.

Variables do not exhibit this behaviour; variables behave just like variables do in any software language. When a line of code is encountered with a variable assignment (:=), the variable is updated immediately and so its value is immediately available for further calculations.

那么，如何将 cnt 更改为变量:

So, how about changing cnt to a variable:

architecture behav of Bitcount is
  use ieee.numeric_std.all;
begin 
  Countproc:process(clk) 
    variable cnt : count_type;
  begin
    if (clk'event and clk='1' ) then
      if Enable='1' then
        if (Read_bit='1') then
          cnt := (others=> (others=>'0'));
          for k in 0 to 15 loop
            for i in 0 to 15 loop
              if ( Ram(k) = std_logic_vector(to_unsigned(i, 4)) )then         
                cnt (i) := cnt (i) + "01";
              end if;
            end loop;
          end loop;
          Count <= cnt;
        end if;
      end if;
    end if;
  end process Countproc;
end behav;

我不能确定这会起作用，因为你没有提供 MCVE，所以我没有测试它.但是由于我给出的原因，您原来的解决方案将不起作用.

I can't be sure this will work, because you haven't provided an MCVE, so I haven't tested it. But you original solution will not work for the reason I have given.

--

* 这几乎总是正确的，因为 VHDL 将延迟建模为惯性延迟的方式，并且在这个例子中肯定是正确的.但严格来说并非总是如此.

* this is nearly always true, because of the way that VHDL models delays as inertial delays and it is certainly true in this example. But strictly it's not always true.

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