vhdl“表达式不是常数" [英] vhdl "expression is not constant"

问题描述

我确实有以下 vhdl 代码，该代码为 signal FiltReg" 行提供了错误表达式不是常量":

I do have following vhdl code which gives an error "expression is not constant" for the line "signal FiltReg":

--FILE A--
PORT
(
FindParam   : OUT STD_LOGIC_VECTOR(48 DOWNTO 0);
...
);

ARCHITECTURE a OF b IS
SIGNAL MAtaps : STD_LOGIC_VECTOR(4 DOWNTO 0);

BEGIN
FindParam <= (MAtaps & ...);

PROCESS (clk, clr_n)
  BEGIN
  IF clr_n = '0' THEN
    MAtaps <= (OTHERS => '0');
  ELSIF (clk'EVENT AND clk = '1') THEN
    MAtaps <= param2((MAtaps'HIGH) DOWNTO 0); 
  END IF;
END PROCESS;

.

 --FILE B--
 PORT
 (
 FindParam   : in STD_LOGIC_VECTOR(48 DOWNTO 0);
 ...
 );

 -- Local signals
   signal MAtaps     : integer range 0 to 16;
   signal FiltReg    : UNSIGNED(MAtaps DOWNTO 0); 


BEGIN

    MAtaps <= to_integer(unsigned(FindParam(48 DOWNTO 44)));

看起来信号声明必须是常量，但事实并非如此.

It looks like the signal declaration has to be constant which is not the case.

问题:是否有解决方案或变通方法可以将 MAtaps 用于信号 FiltReg 声明?

Question: Is there a solution or workaround in order to use MAtaps for the signal FiltReg declaration?

Quartus 错误消息是:

The Quartus error message is:

提前致谢

推荐答案

没有.MAtaps 需要static，即在编译时固定.(VHDL 是一种硬件描述语言.您不能拥有可变数量的硬件.)MAtaps 可以是常量或泛型，但不能是另一种信号或变量.

No. MAtaps needs to be static, that is, fixed at compile time. (VHDL is a hardware description language. You can't have a variable amount of hardware.) MAtaps can be a constant or a generic, but it can't be another signal or a variable.

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