“模板"VHDL 实体 [英] "template" VHDL entities

问题描述

这让我困扰了很长一段时间，但是否有可能在 VHDL 中描述实体类似于 C++ 中模板的工作方式(或较少扩展泛型?).只是让实际的端口类型只在综合/编译期间决定?

This has me bugging for quite some time, but is it possible to describe entities in VHDL similar to how templates work in C++ (or to lesser extend generics?). Simply leaving the actual port types to be only decided during synthesize/compilation?

一个例子是多路复用器，假设我有一个 4 输入多路复用器，现在我有几个总线大小我使用这个多路复用器，-4,6,7,8-.目前我为每个不同的总线大小编写了一个不同的多路复用器；然而，输出只是转发的选定输入之一，因此与总线类型相同.

An example would be a multiplexer, say I have a 4 input multiplexer, now I have several bus sizes I use this multiplexer for, -4,6,7,8-. Currently I wrote a different multiplexer for each different bus size; however the output is simply one of the chosen inputs forwarded, and is thus of the same type as the bus.

这似乎过于冗余且容易出错(在正确的时间选择正确的多路复用器，使它们保持一致，并在我更改总线大小时更新它们).有没有办法参数化这个?

This seems overly redundant and error prone (choose correct multiplexer at correct times, keep them all in line, update them as I change the bus size). Is there no way to parameterize this?

下面的非通用版本来展示这个想法.

non generic version below to show the idea.

entity mux_6bit_4input is
    port (  input_0 : in    std_logic_vector (5 downto 0);
        input_1 : in    std_logic_vector (5 downto 0);
        input_2 : in    std_logic_vector (5 downto 0);
        input_3 : in    std_logic_vector (5 downto 0);
        sel : in    std_logic_vector (1 downto 0);
        output  : out   std_logic_vector (5 downto 0)
    );
end entity mux_6bit_4input;

推荐答案

也许我误解了这个问题，但是使用泛型的通用解决方案是否解决了您的问题?

Maybe I misunderstood the question, but doesn't the common solution using generics solve your problem?

library ieee;
use ieee.std_logic_1164.all;

entity mux_4x1 is
    generic (
        DATA_WIDTH: integer := 8
    );
    port (
        input_0: in std_logic_vector(DATA_WIDTH-1 downto 0);
        input_1: in std_logic_vector(DATA_WIDTH-1 downto 0);
        input_2: in std_logic_vector(DATA_WIDTH-1 downto 0);
        input_3: in std_logic_vector(DATA_WIDTH-1 downto 0);
        sel: in std_logic_vector (1 downto 0);
        output: out std_logic_vector(DATA_WIDTH-1 downto 0)
    );
end;

architecture behavior of mux_4x1 is
begin
    output <=
        input_0 when sel = "00" else
        input_1 when sel = "01" else
        input_2 when sel = "10" else
        input_3;
end;

另一个解决方案，如果你想保持真正通用，是使用 VHDL-2008 中很酷的通用类型.我的模拟器尚不支持此功能，因此这里是优秀书籍 VHDL 2008:只是新东西:

Another solution, if you want to keep things really generic, is to use the cool generic types in VHDL-2008. My simulator doesn't yet support this feature, so here's an example from the excellent book VHDL 2008: Just the New Stuff:

entity generic_mux2 is
    generic (type data_type);
    port (
        sel: in bit;
        a, b: in data_type;
        z: out data_type
    );
end;

architecture rtl of mux2 is
begin
    z <= a when sel = '0' else b;
end;

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