尝试在 VHDL 中使用缓冲区 - 不起作用 [英] Trying to use a buffer in VHDL - not working
问题描述
我的代码在编译时产生以下错误:
My code produces the following error when compiling:
ERROR:HDLCompiler:439 - E:/ELECTRONIC ENGINEERING 2/DIGITAL/Resit_Year/Assignment_7_seg/4_Bit_Counter/Bit_Counter/counter_tb.vhd"第 47 行:模式缓冲区的正式端口 count_out 不能与模式输出的实际端口 count_out 相关联错误:模拟器:777 - 库工作中顶级 VHDL 设计单元 counter_tb 的静态细化失败
ERROR:HDLCompiler:439 - "E:/ELECTRONIC ENGINEERING 2/DIGITAL/Resit_Year/Assignment_7_seg/4_Bit_Counter/Bit_Counter/counter_tb.vhd" Line 47: Formal port count_out of mode buffer cannot be associated with actual port count_out of mode out ERROR:Simulator:777 - Static elaboration of top level VHDL design unit counter_tb in library work failed
不知道如何解决这个问题.
don't know how to fix this.
完整代码:
-----------------------------------------------------------------------------------
entity Four_Bit_Counter is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
pause : in STD_LOGIC;
count_out : buffer STD_LOGIC_VECTOR (3 downto 0);
student_id : buffer STD_LOGIC_VECTOR (3 downto 0) );
end Four_Bit_Counter;
----------------------------------------------------------------------------------
architecture Behavioral of Four_Bit_Counter is
signal temp_count : std_logic_vector(3 downto 0) := "0000" ;
signal slow_clock : std_logic ;
signal clock_divider : std_logic_vector(1 downto 0) := "00";
variable cout_out : std_logic_vector(3 downto 0):= "0000";
begin
---------------------------------------------------------------------------------
clock_division : process (clock, clock_divider)
begin
if
clock'event and clock = '1' then
clock_divider <= clock_divider + 1;
end if;
slow_clock <= clock_divider(1);
end process;
--------------------------------------------------------------------------------
counting : process(reset, pause, slow_clock, temp_count)
begin
if reset = '1' then
temp_count <= "0000";
elsif pause = '1' then
temp_count <= temp_count;
else
if slow_clock'event and slow_clock= '1' then
if temp_count < 15 then
temp_count <= temp_count + 1;
else
temp_count <= "0000";
end if;
end if;
end if;
count_out <= temp_count;
end process;
----------------------------------------------------------------------------------
student : process (reset, pause, slow_clock, temp_count)
begin
IF (cout_out = "0010") THEN
student_id <= "0010";
ELSIF (cout_out = "0011") THEN
student_id <= "0001";
ELSIF (cout_out = "0100") THEN
student_id <= "0000";
ELSIF (cout_out = "0101") THEN
student_id <= "0000";
ELSIF (cout_out = "0110") THEN
student_id <= "1001";
ELSIF (cout_out = "0111") THEN
student_id <= "0011";
ELSIF (cout_out = "1000") THEN
student_id <= "0010";
ELSIF (cout_out = "1001") THEN
student_id <= "0110";
ELSE student_id <= "1000";
END IF;
end process student;
--student_id <= "0010" when count_out >= "0001" else
--"0001" when count_out >= "0011" else
--"0000" when count_out >= "0101" else
--"0000" when count_out >= "0111" else
--"1001" when count_out >= "1000" else
--"0011" when count_out >= "1001" else
--"0000" when count_out >= "1011" else
--"0110" when count_out >= "1100" else
--"1000";
end Behavioral;
推荐答案
Old style VHDL : Buffer 端口必须连接到 Buffer 端口(不是 Out 端口)一直到层次结构.这背后的原因在 VHDL 的早期是有道理的，但 ASIC 和 FPGA 技术已经发展，综合技术也是如此.
Old style VHDL : Buffer ports must be connected to Buffer ports (not Out ports) all the way up the hierarchy. The reason behind this made sense in the early days of VHDL but ASIC and FPGA technology has moved on, so has synthesis technology.
旧式解决方案:因此在实体中制作 out 端口(您没有发布足够的代码，因此我无法命名它，但它是层次结构中的下一个级别)一个 buffer 端口也是.
Old style solution : So make the out port in entity (you haven't posted enough code so I can't name it, but it's the next level up in the hierarchy) a buffer port too.
解决方法:如果不允许在更高级别更改端口类型，则可以将 Buffer 端口连接到一个信号，并将该信号分配给 out 端口.
Workaround : If you're not allowed to change the port type in the higher level, you can connect the Buffer port to a signal, and assign that signal to the out port.
较新的 VHDL:在 VHDL-2002 中消除了此限制，因此如果您在编译时选择 --std=vhdl2002 或等效选项，这应该可以工作.
Newer VHDL : in VHDL-2002 this restriction was eliminated, so this should work if you select --std=vhdl2002 or equivalent option when compiling.
最新的 VHDL :因为 Buffer 的教导太差，所以造成了很多混乱，如果你选择 --std=vhdl2008，out 端口现在允许读取驱动值，就像 buffer 端口一样，因此您可以简单地将 buffer 端口替换为 out 端口.
Newest VHDL : Because Buffer has been so poorly taught it's created so much confusion, that if you select --std=vhdl2008, out ports now allow reading the driving value just like buffer ports, so you can simply replace your buffer ports with out ports.
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