ARM cortex:使用位带的互斥锁 [英] ARM cortex: mutex using bit banding

问题描述

鉴于在 ARM Cortex M3 上，我可以:

Given that, on the ARM Cortex M3, I can:

• 原子读取一个位
• 原子地设置一个位
• 原子清除单个位

如何将这些组合用于互斥样式的操作集:

How can I combine these for a mutex style set of operations:

try lock
take lock
release lock

try_lock 或 take_lock 似乎需要两个不是原子的操作.

It seems that try_lock or take_lock would require two operations that would not be atomic.

我是否需要更多控制来完成此操作?禁用全局中断可以做到这一点，但似乎应该有更外科手术的方法.

Do I need more control to accomplish this? Disable global interrupts would do it but it seems there should be a more surgical approach.

推荐答案

你的 rwl_TryLock() 如果在调用时已经持有锁(你的编译器应该给出至少是关于没有返回值的代码路径的警告).请尝试以下操作:

Your rwl_TryLock() doesn't necessarily return a failure if the lock is already held when it's called (your compiler should be giving at least a warning about a code path that has no return value). Try the following:

int rwl_TryLock(volatile uint32_t *lock, int who){

    Var_SetBit_BB((uint32_t)lock, who);
    if(*lock == (1<<who)){ // check that we have exclusive access
        // got the lock!
        return 1;
    } 

    // do not have the lock
    Var_ResetBit_BB((uint32_t)lock, who); // clear the lock flag
    return 0;
}

请注意，上面的代码不适用于递归声明相同的锁(即，如果 who == 1 指定的任务已经拥有该锁并尝试再次声明它，则上面的代码将无法正常工作)，但您的原件也是如此.

Note that the above will not work for recursively claiming the same lock (ie., if the task specified by who == 1 already has the lock and tries to claim it again, the code above will not work correctly), but that was true of your original as well.

此外，可以很快地在 Cortex M3 上禁用/启用中断(这是对 NVIC 寄存器的简单更新).您确定您的系统不能承受额外的几个中断延迟周期以保持处理锁数据结构的代码简单(这通常意味着更容易更正)?

Also, interrupts can be disabled/enabled on the Cortex M3 pretty quickly (it's a simple update to an NVIC register). Are you sure your system can't live with an additional few cycles of interrupt latency to keep the code for handling the lock data structures simple (which generally means easier to make correct)?

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