aarch64;Load-Acquire Exclusive vs Load Exclusive [英] aarch64; Load-Acquire Exclusive vs Load Exclusive

问题描述

LDAXR 和有什么区别?LDXR 指令超出 AArch64 指令集?

What is the difference between LDAXR & LDXR instructions out of AArch64 instruction set?

从参考手册来看，它们看起来完全一样(除了获取"这个词):

From reference manual they looks totally the same (with exception of 'acquire' word):

LDAXR - Load-Acquire Exclusive Register:从由基址寻址的存储器加载字到 Wt.记录物理地址为独占访问.

LDAXR - Load-Acquire Exclusive Register: loads word from memory addressed by base to Wt. Records the physical address as an exclusive access.

LDXR - 加载独占寄存器:从内存中加载一个字，由基址寻址到 Wt.记录物理地址为独占访问.

LDXR - Load Exclusive Register: loads a word from memory addressed by base to Wt. Records the physical address as an exclusive access.

谢谢

推荐答案

最简单的形式，LDAEX == LDXR +DMB_SY.

In the simplest form, LDAEX == LDXR +DMB_SY.

这是我为 LDAXR 找到的描述:

This is the description which I find for LDAXR:

C6.2.104 LDAXR

加载-获取独占寄存器从基址派生地址寄存器值，从内存加载 32 位字或 64 位双字，并将其写入寄存器.内存访问是原子的.PE标志作为独占访问访问的物理地址.这个独占访问标记由 Store Exclusive 指令检查.看第 B2-135 页的同步和信号量.该指令还具有 Load-Acquire 中描述的内存排序语义，加载-获取PC 和存储-发布(第 B2-108 页).信息关于内存访问，请参阅第 C1-157 页上的加载/存储寻址模式.

Load-Acquire Exclusive Register derives an address from a base register value, loads a 32-bit word or 64-bit doubleword from memory, and writes it to a register. The memory access is atomic. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores on page B2-135. The instruction also has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release on page B2-108. For information about memory accesses see Load/Store addressing modes on page C1-157.

来自 DDI0487 Da

ARMv8 架构增加了获取和释放语义Load-Exclusive 和 Store-Exclusive 指令，允许它们获得排序获取和/或释放语义.负载独占可以指定指令具有获取语义，并且可以指定 Store-Exclusive 指令进行发布语义.这些可以任意组合以允许原子由成功的 Load-Exclusive 和 Store-Exclusive 对创建的更新拥有以下任何一项:

The ARMv8 architecture adds the acquire and release semantics to Load-Exclusive and Store-Exclusive instructions, which allows them to gain ordering acquire and/or release semantics. The Load-Exclusive instruction can be specified to have acquire semantics, and the Store-Exclusive instruction can be specified to have release semantics. These can be arbitrarily combined to allow the atomic update created by a successful Load-Exclusive and Store-Exclusive pair to have any of:

• 无排序语义(使用 LDREX 和 STREX).

• No Ordering semantics (using LDREX and STREX).

仅获取语义(使用 LDAEX 和 STREX).

Acquire only semantics (using LDAEX and STREX).

仅发布语义(使用 LDREX 和 STLEX).

Release only semantics (using LDREX and STLEX).

顺序一致的语义(使用 LDAEX 和 STLEX).

Sequentially consistent semantics (using LDAEX and STLEX).

还有(B2.3.5)，

Also (B2.3.5),

一条Load-Acquire指令的基本原理是引入Load-Acquire 生成的内存访问之间的顺序指令和内存访问出现在程序顺序之后Load-Acquire 指令，使得内存访问由Load-Acquire 指令被每个 PE 观察到该 PE 需要一致地观察访问，在任何之前出现在程序顺序之后的内存访问加载-获取指令被那个 PE 观察到，在一定程度上要求PE一致地观察访问.

The basic principle of a Load-Acquire instruction is to introduce order between the memory access generated by the Load-Acquire instruction and the memory accesses appearing in program order after the Load-Acquire instruction, such that the memory access generated by the Load-Acquire instruction is Observed-by each PE, to the extent that that PE is required to observe the access coherently, before any of the memory accesses appearing in program order after the Load-Acquire instruction are Observed-by that PE, to the extent that the PE is required to observe the accesses coherently.

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