stp aarch64 指令必须与“非连续寄存器对"一起使用； [英] stp aarch64 instruction must be used with "non-contiguous pair of registers"
问题描述
aarch64 架构没有用于多重存储和加载的指令，即没有来自 armv7 arch 的 stm 和 ldm 的等价物.相反，您必须使用 stp 和 ldp 指令来存储和加载寄存器对.
The aarch64 architecture doesn't have instructions for multiple store and load, i.e. there are no equivalents of stm and ldm from armv7 arch. Instead you must use the stp and ldp instructions for store and loading pairs of registers.
根据 ARM 参考手册:
Accroding to the ARM reference manual:
没有多寄存器 LDM、STM、PUSH 和 POP 指令，但可以使用非>连续寄存器对的加载存储.
There are no multiple register LDM, STM, PUSH and POP instructions, but load-store of a non-> contiguous pair of registers is available.
我的问题是，这里的非连续意味着或指的是什么?我的即时反应是，这意味着您不能在这些命令中使用连续编号的寄存器，例如
My question is, what does non-contiguous mean or refer to here? My instant reaction was that it means you can't use consecutively numbered registers with these commands, e.g.
stp x0, x1, [sp, #-16]!
是非法的.但是，我不相信情况是这样.我已经看到示例代码正是这样做的，而且我已经设法让(Apple 的)Clang 生成类似的代码，例如
is illegal. However I don't believe this is the case. I've seen example code doing exactly this and furthermore I've managed to get (Apple's) Clang to generate similar code, e.g.
stp x1, x0, [fp, #-16]!
我一生都无法思考连续意味着什么.我认为这可能与使用重叠寄存器有关，例如
I can't for the life of me think what contiguous then means. I thought it could be something to do with using overlapping registers, e.g.
stp x0, x0, [sp, #-16]!
stp w0, x0, [sp, #-12]!
不过，我也看到过这样的示例代码(并不是说代码是正确的！).此外，如果是这种情况，我会明确使用重叠而不是连续的术语.
However I've seen example code doing this sort of things as well (not to say that code was correct!). Also I would have explicitly used the terminology overlapping rather than contiguous if this were the case.
有什么想法吗?
推荐答案
它主要突出与 A32 (ARM) LDRD/STRD 指令*，只能加载一对连续的寄存器，其中最低的必须是偶数，即:
It is primarily highlighting the contrast with the A32 (ARM) LDRD/STRD instructions*, which can only load a consecutive pair of registers, the lowest of which must be even-numbered, i.e.:
LDRD r0, r1, [sp] @ OK
LDRD r0, r7, [sp] @ <Rt> and <Rt2> are non-contiguous: invalid
LDRD r3, r4, [sp] @ Contiguous but <Rt> odd-numbered: invalid
[这是因为指令中只有一个空间来编码一个目标寄存器，所以架构必须有一种定义的方式来推断第二个目标寄存器.]
[This is down to the fact that there's only space to encode one target register in the instruction, so the architecture must have a defined way of inferring the second target register.]
相比之下，A64 LDP/STP 编码有空间对两个目标寄存器进行编码，这意味着它们可以是任意顺序的任意两个寄存器，即它们被允许不连续 - 这是一种许可，而不是一种限制.
In contrast, the A64 LDP/STP encodings have room to encode two target registers, which means they can be any two registers in any order, i.e. they are allowed to be non-contiguous - it's a permission, not a restriction.
请注意，该特定文档已过时 自发布完整的 ARMv8 ARM，它有适当的详细说明页面，应该稍微不那么模糊.
Note that that particular document is obsolete since the release of the full ARMv8 ARM, which has proper detailed instruction pages that should be slightly less ambiguous.
* T32 (Thumb) 编码没有这个限制，因为缺少条件谓词意味着有空间来编码第二个目标寄存器，很像 A64.
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