STP aarch64指令必须与使用QUOT;非连续对寄存器＆QUOT的; [英] stp aarch64 instruction must be used with "non-contiguous pair of registers"

问题描述

的aarch64架构不具有多存储和加载，即，不存在从ARMv7的拱STM和LDM的等同指令。相反，你必须使用STP和LDP指令存储和装载寄存器对的。

The aarch64 architecture doesn't have instructions for multiple store and load, i.e. there are no equivalents of stm and ldm from armv7 arch. Instead you must use the stp and ldp instructions for store and loading pairs of registers.

Accroding到ARM参考手册：

Accroding to the ARM reference manual:

<一个href=\"http://www.element14.com/community/servlet/JiveServlet/$p$pviewBody/41836-102-1-229511/ARM.Reference_Manual.pdf\" rel=\"nofollow\">http://www.element14.com/community/servlet/JiveServlet/$p$pviewBody/41836-102-1-229511/ARM.Reference_Manual.pdf

有没有多寄存器LDM，STM，PUSH和POP指令，但非>连续对寄存器的负载店。

There are no multiple register LDM, STM, PUSH and POP instructions, but load-store of a non-> contiguous pair of registers is available.

我的问题是，什么是不连续的均值或参考这里？我的即时反应是，这意味着你不能用这些命令使用连续编号的寄存器，例如

My question is, what does non-contiguous mean or refer to here? My instant reaction was that it means you can't use consecutively numbered registers with these commands, e.g.

stp x0, x1, [sp, #-16]!

是非法的。不过，我不相信这是事实。我见过例如code做的正是这一点，而且我已经成功地得到（苹果）锵产生类似code，例如

is illegal. However I don't believe this is the case. I've seen example code doing exactly this and furthermore I've managed to get (Apple's) Clang to generate similar code, e.g.

stp x1, x0, [fp, #-16]!

我不能为我的生活怎么想的连续再手段。我想这可能是一些做与使用重叠的寄存器，例如

I can't for the life of me think what contiguous then means. I thought it could be something to do with using overlapping registers, e.g.

stp x0, x0, [sp, #-16]!
stp w0, x0, [sp, #-12]!

不过，我已经看到了例如code做这种事情，以及（不是说code是正确的！）。我还必须明确所使用的术语重叠的，而不是连续的，如果是这样的话。

However I've seen example code doing this sort of things as well (not to say that code was correct!). Also I would have explicitly used the terminology overlapping rather than contiguous if this were the case.

任何想法？

推荐答案

它主要强调与A32（ARM）的对比度<一个href=\"http://infocenter.arm.com/help/topic/com.arm.doc.dui0802a/CIHGJHED.html\"><$c$c>LDRD/<$c$c>STRD说明*，这只能加载连续对寄存器，其中最低的必须偶数，即：

It is primarily highlighting the contrast with the A32 (ARM) LDRD/STRD instructions*, which can only load a consecutive pair of registers, the lowest of which must be even-numbered, i.e.:

LDRD r0, r1, [sp]   @ OK
LDRD r0, r7, [sp]   @ <Rt> and <Rt2> are non-contiguous: invalid
LDRD r3, r4, [sp]   @ Contiguous but <Rt> odd-numbered: invalid

[这是下降到一个事实，即有只为en $ C $空间中的c指令一个目标寄存器，因此结构必须有一个定义推断第二目标寄存器的方式。]

[This is down to the fact that there's only space to encode one target register in the instruction, so the architecture must have a defined way of inferring the second target register.]

在相反，A64 <一href=\"http://infocenter.arm.com/help/topic/com.arm.doc.dui0802a/LDP_gen.html\"><$c$c>LDP/<$c$c>STP编码有房EN code两个目标寄存器，这意味着它们可以以任意顺序任意两个寄存器，即它们的允许的是不连续的 - 这是一个许可，不限制

In contrast, the A64 LDP/STP encodings have room to encode two target registers, which means they can be any two registers in any order, i.e. they are allowed to be non-contiguous - it's a permission, not a restriction.

请注意该特定文件是过时自发布完整的 ARMv8的ARM ，该有适当的详细说明该页面应该略少模棱两可。

Note that that particular document is obsolete since the release of the full ARMv8 ARM, which has proper detailed instruction pages that should be slightly less ambiguous.

<子> *的T32（拇指）编码没有这个限制，因为缺一个条件predicate意味着有空间EN code中的第二个目标寄存器，很像A64。

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