什么是传统中断? [英] What are legacy interrupts?
问题描述
我正在从事一个项目，我试图弄清楚如何在 ARM 架构的全局中断控制器中处理中断.我正在使用 pl390 中断控制器.我看到有一行被称为绕过分发器逻辑的遗留中断.假设可以将 2 个中断编程为传统中断.任何人都可以帮助解释什么是遗留中断?我尝试在线搜索但没有任何运气.
I am working on a project where i am trying to figure out how an interrupt is processed in the Global interrupt controller for a ARM architecture. I am working with pl390 interrupt controller. I see there is a line which is mentioned as legacy interrupts which bypasses the distributor logic. It is given that 2 interrupts can be programmed as a legacy interrupt. Can any one help with some explanation of what exactly is a legacy interrupt?. I trying searching online without any luck.
推荐答案
遗留中断是 GIC 到达之前 ARM 中的两个中断:nIRQ - 正常中断请求，和 fIRQ - 快速中断请求.
Legacy interrupts are the two interrupts that were in ARM before GIC arrived: nIRQ - normal interrupt request, and fIRQ - fast interrupt request.
由于旧式中断是为单核处理器制作的，并且它们内部不支持多核处理器，因此它们绕过分发器逻辑的原因应该很清楚 - 旧式中断硬连线到其中一个内核中.
Since legacy interrupts were made for single-core processors, and they don't support multi-core processors internally, the reason they bypass the distributor logic should be rather clear - the legacy interrupts are hardwired into one of the cores.
简而言之 - 它允许 CPU 向后兼容旧的 ARM 规范.例如，一个四核 ARM CPU 将有 4 个 nIRQ 和 4 个 fIRQ，每个内核是分开的.当您有一块旧的 ARM 兼容硬件(不支持 GIC)时，您将其连接到内核的 nIRQ/fIRQ 之一，就像将其连接到旧的单核 CPU 一样，它会始终执行在那个核心上.
In short - it allows the CPU to work in backwards compatibility with older ARM specification. For example, a four-core ARM CPU will have 4 nIRQs and 4 fIRQs, separate for each of the cores. When you have an old piece of ARM-compatible hardware (which doesn't support GIC), you connect it to one of the core's nIRQ/fIRQ just as if you connected it to an old single-core CPU, and it will always execute on that one core.
可以在此处找到更多信息 - http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407e/CCHDBEBE.html
More information can be found here - http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407e/CCHDBEBE.html
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