什么是传统的中断？ [英] What are legacy interrupts?

问题描述

我工作的一个项目，我试图找出中断是如何在一个ARM架构的全局中断控制器处理。我与pl390中断控制器工作。我看到有被提到绕过经销商逻辑遗留中断线路。这是因为2个中断源可以编程为一个传统的中断。任何一个可以帮助拥有究竟是一个传统的中断一些解释？我想没有任何运气在线搜索。

I am working on a project where i am trying to figure out how an interrupt is processed in the Global interrupt controller for a ARM architecture. I am working with pl390 interrupt controller. I see there is a line which is mentioned as legacy interrupts which bypasses the distributor logic. It is given that 2 interrupts can be programmed as a legacy interrupt. Can any one help with some explanation of what exactly is a legacy interrupt?. I trying searching online without any luck.

推荐答案

传统中断的均GIC之前，ARM的两个中断到来：nIRQ失效 - 正常的中断请求，fIRQ - 快速中断请求

Legacy interrupts are the two interrupts that were in ARM before GIC arrived: nIRQ - normal interrupt request, and fIRQ - fast interrupt request.

由于传统的中断都为单核处理器完成，他们不支持多核心处理器在内部，他们绕过经销商的逻辑应该是相当清楚的原因 - 传统中断硬连接至核心之一

Since legacy interrupts were made for single-core processors, and they don't support multi-core processors internally, the reason they bypass the distributor logic should be rather clear - the legacy interrupts are hardwired into one of the cores.

在短期 - 它允许CPU在向后兼容性工作与旧的ARM规范。例如，一个四芯ARM CPU将有4 nIRQs和4 fIRQs，单独为每个核。当你有一块旧ARM兼容的硬件（不支持GIC），将其连接到就像如果你将它连接到一个单核CPU内核的nIRQ失效/ fIRQ之一，它总会执行上一个核心。

In short - it allows the CPU to work in backwards compatibility with older ARM specification. For example, a four-core ARM CPU will have 4 nIRQs and 4 fIRQs, separate for each of the cores. When you have an old piece of ARM-compatible hardware (which doesn't support GIC), you connect it to one of the core's nIRQ/fIRQ just as if you connected it to an old single-core CPU, and it will always execute on that one core.

更多信息可以在这里找到 - 的http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407e/CCHDBEBE.html

More information can be found here - http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407e/CCHDBEBE.html

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