浮点分频器硬件实现细节 [英] Floating Point Divider Hardware Implementation Details
问题描述
我正在尝试在硬件中实现一个 32 位浮点硬件除法器，我想知道是否可以就不同算法之间的某些权衡得到任何建议?
我的浮点单元目前支持乘法和加法/减法，但我不打算将它切换到融合乘加 (FMA) 浮点架构，因为这是一个嵌入式平台，我试图在其中最小化面积使用.
很久以前，我遇到了这个在那个时期的军事 FPU 中使用的简洁且易于实现的浮点/定点除法算法:
>
输入必须是无符号的并被移位，所以
x< 范围内0.5 ;1 >不要忘记存储移位
sh = shx - shy和原始符号的差异find
f(通过迭代)所以y*f ->1.... 之后x*f ->x/y即除法结果将
x*f移回sh并恢复结果符号(sig=sigx*sigy)x*f可以像这样轻松计算:z=1-y(x*f)=(x/y)=x*(1+z)*(1+z^2)*(1+z^4)*(1+z^8)*(1+z^16)...(1+z^2n)哪里
n = log2(定点的小数位数，或浮点的尾数位大小)您也可以在固定位宽数据类型的
z^2n为零时停止.
[Edit2] 有一点时间和心情，所以这里是 32 位 IEEE 754 C++ 实现
我删除了旧的(bignum)示例以避免给未来的读者造成混淆(如果需要，它们仍然可以在编辑历史中访问)
//---------------------------------------------------------------------//IEEE 754 单掩码const DWORD _f32_sig =0x80000000;//标志const DWORD _f32_exp =0x7F800000;//指数const DWORD _f32_exp_sig=0x40000000；//指数符号const DWORD _f32_exp_bia=0x3F800000；//指数偏差const DWORD _f32_exp_lsb=0x00800000;//指数 LSBconst DWORD _f32_exp_pos= 23;//指数 LSB 位位置const DWORD _f32_man = 0x007FFFFF;//尾数const DWORD _f32_man_msb=0x00400000；//尾数 MSBconst DWORD _f32_man_bits= 23;//尾数位//---------------------------------------------------------------------------浮动 f32_div(浮动 x，浮动 y){union _f32//浮点位访问{浮动 f;//32位浮点数双字你;//32 位单位};_f32 xx,yy,zz;国际 sh;双字 zsig;浮动 z;//结果符号绝对值xx.f=x;zsig =xx.u&_f32_sig;xx.u&=(0xFFFFFFFF^_f32_sig);yy.f=y;zsig^=yy.u&_f32_sig;yy.u&=(0xFFFFFFFF^_f32_sig);//初始指数差 sh 并归一化指数以加速范围内的移动sh = 0;sh-=((xx.u&_f32_exp)>>_f32_exp_pos)-(_f32_exp_bia>>_f32_exp_pos);xx.u&=(0xFFFFFFFF^_f32_exp);xx.u|=_f32_exp_bia;sh+=((yy.u&_f32_exp)>>_f32_exp_pos)-(_f32_exp_bia>>_f32_exp_pos);yy.u&=(0xFFFFFFFF^_f32_exp);yy.u|=_f32_exp_bia;//在范围内移动输入而 (xx.f> 1.0f) { xx.f*=0.5f;嘘——；}而 (xx.f<0.5f) { xx.f*=2.0f;sh++;}而 (yy.f> 1.0f) { yy.f*=0.5f;sh++;}而 (yy.f< 0.5f) { yy.f*=2.0f;嘘——；}而 (xx.f<=yy.f) { yy.f*=0.5f;sh++;}//分隔块z=(1.0f-yy.f);zz.f=xx.f*(1.0f+z);为了 (;;){z*=z;如果 (z==0.0f) 中断；zz.f*=(1.0f+z);}//将结果移回for (;sh>0;) { sh--;zz.f*=0.5f;}for (;sh<0;) { sh++;zz.f*=2.0f;}//设置符号zz.u&=(0xFFFFFFFF^_f32_sig);zz.u|=zsig;返回 zz.f;}//---------------------------------------------------------------------------我想保持简单，所以它尚未优化.例如，您可以将所有 *=0.5 和 *=2.0 替换为指数 inc/dec ... 如果您与 *=0.5 上的 FPU 结果进行比较code>float operator / 这会有点不精确，因为大多数 FPU 在 80 位内部格式上计算，而此实现仅在 32 位上.
如您所见，我从 FPU 中仅使用 +,-,*.这些东西可以通过使用像
特别是如果你想使用大的位宽...
不要忘记实施规范化和/或上溢/下溢校正.
I am trying to implement a 32-bit floating point hardware divider in hardware and I am wondering if I can get any suggestions as to some tradeoffs between different algorithms?
My floating point unit currently suppports multiplication and addition/subtraction, but I am not going to switch it to a fused multiply-add (FMA) floating point architecture since this is an embedded platform where I am trying to minimize area usage.
Once upon a very long time ago i come across this neat and easy to implement float/fixed point divison algorithm used in military FPUs of that time period:
input must be unsigned and shifted so
x < yand both are in range< 0.5 ; 1 >don't forget to store the difference of shifts
sh = shx - shyand original signsfind
f(by iterating) soy*f -> 1.... after thatx*f -> x/ywhich is the division resultshift the
x*fback byshand restore result sign(sig=sigx*sigy)the
x*fcan be computed easily like this:z=1-y (x*f)=(x/y)=x*(1+z)*(1+z^2)*(1+z^4)*(1+z^8)*(1+z^16)...(1+z^2n)where
n = log2(num of fractional bits for fixed point, or mantisa bit size for floating point)You can also stop when
z^2nis zero on fixed bit width data types.
[Edit2] Had a bit of time&mood for this so here 32 bit IEEE 754 C++ implementation
I removed the old (bignum) examples to avoid confusion for future readers (they are still accessible in edit history if needed)
//---------------------------------------------------------------------------
// IEEE 754 single masks
const DWORD _f32_sig =0x80000000; // sign
const DWORD _f32_exp =0x7F800000; // exponent
const DWORD _f32_exp_sig=0x40000000; // exponent sign
const DWORD _f32_exp_bia=0x3F800000; // exponent bias
const DWORD _f32_exp_lsb=0x00800000; // exponent LSB
const DWORD _f32_exp_pos= 23; // exponent LSB bit position
const DWORD _f32_man =0x007FFFFF; // mantisa
const DWORD _f32_man_msb=0x00400000; // mantisa MSB
const DWORD _f32_man_bits= 23; // mantisa bits
//---------------------------------------------------------------------------
float f32_div(float x,float y)
{
union _f32 // float bits access
{
float f; // 32bit floating point
DWORD u; // 32 bit uint
};
_f32 xx,yy,zz; int sh; DWORD zsig; float z;
// result signum abs value
xx.f=x; zsig =xx.u&_f32_sig; xx.u&=(0xFFFFFFFF^_f32_sig);
yy.f=y; zsig^=yy.u&_f32_sig; yy.u&=(0xFFFFFFFF^_f32_sig);
// initial exponent difference sh and normalize exponents to speed up shift in range
sh =0;
sh-=((xx.u&_f32_exp)>>_f32_exp_pos)-(_f32_exp_bia>>_f32_exp_pos); xx.u&=(0xFFFFFFFF^_f32_exp); xx.u|=_f32_exp_bia;
sh+=((yy.u&_f32_exp)>>_f32_exp_pos)-(_f32_exp_bia>>_f32_exp_pos); yy.u&=(0xFFFFFFFF^_f32_exp); yy.u|=_f32_exp_bia;
// shift input in range
while (xx.f> 1.0f) { xx.f*=0.5f; sh--; }
while (xx.f< 0.5f) { xx.f*=2.0f; sh++; }
while (yy.f> 1.0f) { yy.f*=0.5f; sh++; }
while (yy.f< 0.5f) { yy.f*=2.0f; sh--; }
while (xx.f<=yy.f) { yy.f*=0.5f; sh++; }
// divider block
z=(1.0f-yy.f);
zz.f=xx.f*(1.0f+z);
for (;;)
{
z*=z; if (z==0.0f) break;
zz.f*=(1.0f+z);
}
// shift result back
for (;sh>0;) { sh--; zz.f*=0.5f; }
for (;sh<0;) { sh++; zz.f*=2.0f; }
// set signum
zz.u&=(0xFFFFFFFF^_f32_sig);
zz.u|=zsig;
return zz.f;
}
//---------------------------------------------------------------------------
I wanted to keep it simple so it is not optimized yet. You can for example replace all *=0.5 and *=2.0 by exponent inc/dec ... If you compare with FPU results on float operator / this will be a bit less precise because most FPUs compute on 80 bit internal format and this implementation is only on 32 bits.
As you can see I am using from FPU just +,-,*. The stuff can be speed up by using fast sqr algorithms like
especially if you want to use big bit widths ...
Do not forget to implement normalization and or overflow/underflow correction.
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