哪些 x86 指令需要两个(或更多)内存操作数? [英] What x86 instructions take two (or more) memory operands?

问题描述

我以为是零.但是，我在这里看到，

具有两个内存操作数的指令极为罕见

Instructions with two memory operands are extremely rare

我找不到任何可以解释存在哪些指令(尽管很少见)的内容.有哪些例外?

I can't find anything that explains what instructions, though rare, exist. What are the exceptions?

推荐答案

我找不到任何可以解释这种稀有性的东西.

I can't find anything that explains the rarity.

一条 x86 指令最多可以有一个 ModR/M + SIB + disp0/8/32.所以有两个显式内存操作数的零指令.

An x86 instruction can have at most one ModR/M + SIB + disp0/8/32. So there are zero instructions with two explicit memory operands.

x86 内存-内存指令都至少有一个 隐式 内存操作数，其位置被放入操作码中，例如访问堆栈的 push 或字符串指令 movs 和 cmps.

The x86 memory-memory instructions all have at least one implicit memory operand whose location is baked in to the opcode, like push which accesses the stack, or the string instructions movs and cmps.

有哪些例外?

我将使用 [mem] 表示 ModR/M 寻址模式，可以是 [rdi], [RIP+whatever]、[ebx+eax*4+1234]，或者任何你喜欢的.

I'll use [mem] to indicate a ModR/M addressing mode which can be [rdi], [RIP+whatever], [ebx+eax*4+1234], or whatever you like.

• push [mem]:读取[mem]，写入隐式[rsp](更新rsp后).
• pop [mem]
• call [mem]:从 [mem] 读取一个新的 RIP，将返回地址压入堆栈.
• movsb/w/d/q:读取DS:(E)SI，写入ES:(E)DI(或64位模式的RSI和RDI).两者都是隐含的；只有 DS 段 reg 是可覆盖的.可与 rep 一起使用.

• cmpsb/w/d/q:读取 DS:(E)SI 和 ES:(E)DI(或在 64 位模式下的 RSI 和 RDI).两者都是隐含的；只有 DS 段 reg 是可覆盖的.可与 repe/repne 一起使用.

• push [mem]: reads [mem], writes implicit [rsp] (after updating rsp).
• pop [mem]
• call [mem]: reads a new RIP from [mem], pushes a return address on the stack.
• movsb/w/d/q: reads DS:(E)SI, writes ES:(E)DI (or in 64-bit mode RSI and RDI). Both are implicit; only the DS segment reg is overridable. Usable with rep.

• cmpsb/w/d/q: reads DS:(E)SI and ES:(E)DI (or in 64-bit mode RSI and RDI). Both are implicit; only the DS segment reg is overridable. Usable with repe / repne.

MPX bndstx mib, bnd: "商店bnd 中的边界和 mib 索引寄存器中指向绑定表条目 (BTE) 的指针值，并使用 mib 的基址进行地址转换."Operation 部分显示了一个负载和一个存储，但我对 MPX 的了解不够深入.

MPX bndstx mib, bnd: "Store the bounds in bnd and the pointer value in the index register of mib to a bound table entry (BTE) with address translation using the base of mib." The Operation section shows a load and a store, but I don't know enough about MPX to grok it.

movdir64b r16/r32/r64, m512.有自己的功能位，在即将到来的 Tremont 中可用 (Goldmont Plus Atom 的继任者).将 64 字节作为具有 64 字节写原子性的直接存储 (WC) 从源内存地址移动到目标内存地址.目标操作数是(对齐的原子)es: /r 来自 ModRM，源是(未对齐的非原子)/m 来自 ModRM.

movdir64b r16/r32/r64, m512. Has its own feature bit, available in upcoming Tremont (successor to Goldmont Plus Atom). Moves 64-bytes as direct-store (WC) with 64-byte write atomicity from source memory address to destination memory address. Destination operand is (aligned atomic) es: /r from ModRM, source is (unaligned non-atomic) the /m from ModRM.

store 使用 write-combining，见说明.这是任何 x86 CPU 供应商第一次保证在 lock cmpxchg16b 之外超过 8 个字节的原子性.但不幸的是，它实际上并不适合多线程，因为它会强制执行类似 NT 的缓存逐出/绕过行为，因此其他内核必须从 DRAM 而不是共享的外部缓存中读取它.

Uses write-combining for the store, see the description. It's the first time any x86 CPU vendor has guaranteed atomicity wider than 8 bytes outside of lock cmpxchg16b. But unfortunately it's not actually great for multithreading because it forces NT-like cache eviction/bypass behaviour, so other cores will have to read it from DRAM instead of a shared outer cache.

AVX2 收集和 AVX512 分散指令是有争议的.他们显然做了多次加载/存储，但所有的指针都来自一个 SIMD 向量(和一个标量基).

AVX2 gather and AVX512 scatter instructions are debatable. They obviously do multiple loads / stores, but all the pointers come from one SIMD vector (and a scalar base).

我没有计算像 pusha、fldenv、xsaveopt、iret 或 enter 嵌套级别 > 1，可以对连续块执行多次存储或加载.

I'm not counting instructions like pusha, fldenv, xsaveopt, iret, or enter with nesting level > 1 that do multiple stores or loads to a contiguous block.

我也不计算 ins/outs 字符串指令，因为它们将内存复制到/从 I/O 空间.I/O 空间不是内存.

I'm also not counting the ins / outs string instructions, because they copy memory to/from I/O space. I/O space isn't memory.

我没有查看 http://felixcloutier.com/x86/index 上的 VMX 或 SGX 说明.html，只是主列表.我不认为我错过了任何，但我当然可以.

I didn't look at VMX or SGX instructions on http://felixcloutier.com/x86/index.html, just the main list. I don't think I missed any, but I certainly could have.

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