CPU TSC fetch 操作，尤其是在多核多处理器环境中 [英] CPU TSC fetch operation especially in multicore-multi-processor environment
问题描述
在 Linux 世界中，要获得纳秒精度的计时器/时钟可以使用:
In Linux world, to get nano seconds precision timer/clockticks one can use :
#include <sys/time.h>
int foo()
{
timespec ts;
clock_gettime(CLOCK_REALTIME, &ts);
//--snip--
}
这个答案 建议使用 asm 方法直接查询带有 RDTSC 指令.
This answer suggests an asm approach to directly query for the cpu clock with the RDTSC instruction.
在多核、多处理器架构中，这个时钟滴答/定时器值如何在多个核/处理器之间同步?我的理解是，在进行固有的击剑时.这种理解是否正确?
In a multi-core, multi-processor architecture, how is this clock ticks/timer value synchronized across multiple cores/processors? My understanding is that there in inherent fencing being done. Is this understanding correct?
你能推荐一些详细解释这一点的文档吗?我对 Intel Nehalem 和 Sandy Bridge 微架构感兴趣.
Can you suggest some documentation that would explain this in detail? I am interested in Intel Nehalem and Sandy Bridge microarchitectures.
编辑
将进程限制为单个内核或 cpu 不是一种选择，因为该进程非常庞大(就消耗的资源而言)并且希望以最佳方式利用包括所有内核和处理器在内的机器中的所有资源.
Limiting the process to a single core or cpu is not an option as the process is really huge(in terms of resources consumed) and would like to optimally utilize all the resources in the machine that includes all the cores and processors.
编辑
感谢您确认 TSC 在内核和处理器之间同步.但我最初的问题是这种同步是如何完成的?是用某种围栏吗?你知道任何公共文件吗?
Thanks for the confirmation that the TSC is synced across cores and processors. But my original question is how is this synchronization done ? is it with some kind of fencing ? do you know of any public documentation ?
结论
感谢所有输入:以下是本次讨论的结论:TSC 在初始化时使用在多处理器/多核系统中的内核和处理器之间发生的 RESET 进行同步.在那之后，每个核心都是独立的.TSC 使用锁相环保持不变，该锁相环将标准化频率变化，从而标准化给定核心内的时钟变化，这就是 TSC 在核心和处理器之间保持同步的方式.
Thanks for all the inputs: Here's the conclusion for this discussion: The TSCs are synchronized at the initialization using a RESET that happens across the cores and processors in a multi processor/multi core system. And after that every Core is on their own. The TSCs are kept invariant with a Phase Locked Loop that would normalize the frequency variations and thus the clock variations within a given Core and that is how the TSC remain in sync across cores and processors.
推荐答案
在较新的 CPU (i7 Nehalem+ IIRC) 上，TSC 在所有内核之间同步并以恒定速率运行.因此，对于单个处理器或单个封装或主板上的多个处理器(！)，您可以依靠同步 TSC.
On newer CPUs (i7 Nehalem+ IIRC) the TSC is synchronzied across all cores and runs a constant rate. So for a single processor, or more than one processor on a single package or mainboard(!) you can rely on a synchronzied TSC.
来自英特尔系统手册 16.12.1
From the Intel System Manual 16.12.1
较新处理器中的时间戳计数器可能支持增强功能，称为不变TSC.处理器对不变 TSC 的支持是由 CPUID.80000007H:EDX[8] 指示.不变的 TSC 将在所有 ACPI 中的恒定速率为 P-、C-.和 T 状态.这是建筑行为向前发展.
The time stamp counter in newer processors may support an enhancement, referred to as invariant TSC. Processors support for invariant TSC is indicated by CPUID.80000007H:EDX[8]. The invariant TSC will run at a constant rate in all ACPI P-, C-. and T-states. This is the architectural behavior moving forward.
在较旧的处理器上，您不能依赖恒定速率或同步.
On older processors you can not rely on either constant rate or synchronziation.
至少在单个封装或主板中的多个处理器上，不变的 TSC 是同步的.TSC 在/RESET 时被重置为零，然后在每个处理器上以恒定速率向前滴答，没有漂移./RESET 信号保证同时到达每个处理器.
At least on multiple processors in a single package or mainboard the invariant TSC is synchronized. The TSC is reset to zero at a /RESET and then ticks onward at a constant rate on each processor, without drift. The /RESET signal is guaranteed to arrive at each processor at the same time.
这篇关于CPU TSC fetch 操作，尤其是在多核多处理器环境中的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！
