CPU读取TSC尤其是在多核多处理器环境下操作 [英] CPU TSC fetch operation especially in multicore-multi-processor environment

问题描述

在Linux世界中，获得纳秒precision定时器/时钟信号可以使用：

In Linux world, to get nano seconds precision timer/clockticks one can use :

#include <sys/time.h>

int foo()
{
   timespec ts;

   clock_gettime(CLOCK_REALTIME, &ts); 
   //--snip--      
}

这个答案建议一个 ASM 办法直接查询CPU时钟与 RDTSC 指令。

This answer suggests an asm approach to directly query for the cpu clock with the RDTSC instruction.

在一个多芯，多处理器体系结构，该时钟是如何蜱多个内核/处理器同步/定时值？我的理解是，在固有的击剑那里正在做。这是理解是否正确？

In a multi-core, multi-processor architecture, how is this clock ticks/timer value synchronized across multiple cores/processors? My understanding is that there in inherent fencing being done. Is this understanding correct?

您能否提供一些文件，将详细解释一下吗？我感兴趣的是英特尔的Nehalem和Sandy Bridge的微架构。

Can you suggest some documentation that would explain this in detail? I am interested in Intel Nehalem and Sandy Bridge microarchitectures.

修改

限制的过程中单核或CPU是不是一种选择，因为该过程是非常巨大的（在所消耗的资源而言），并希望以最佳方式利用的所有资源在包括所有的内核和处理器的机器。

Limiting the process to a single core or cpu is not an option as the process is really huge(in terms of resources consumed) and would like to optimally utilize all the resources in the machine that includes all the cores and processors.

修改

感谢您的TSC跨内核和处理器同步确认。但我原来的问题是这是怎么做到同步？它是具有某种围栏？你知道任何公开的文档？

Thanks for the confirmation that the TSC is synced across cores and processors. But my original question is how is this synchronization done ? is it with some kind of fencing ? do you know of any public documentation ?

结论

对于所有的输入感谢：这里的结论，这个讨论：TSC的使用横跨内核和处理器发生在一个多处理器/多核心系统复位在初始化同步。而在这之后的每核心是靠自己。该TSC的保持不变的锁相环一次阶段，将归一化频率的变化，从而给定的核心内的时钟变化的那就是如何TSC留在跨内核和处理器同步。

Thanks for all the inputs: Here's the conclusion for this discussion: The TSCs are synchronized at the initialization using a RESET that happens across the cores and processors in a multi processor/multi core system. And after that every Core is on their own. The TSCs are kept invariant with a Phase Locked Loop that would normalize the frequency variations and thus the clock variations within a given Core and that is how the TSC remain in sync across cores and processors.

推荐答案

在新的CPU（酷睿i7的Nehalem + IIRC）的TSC在所有核心synchronzied并运行一个恒定的速率。
因此，对于一个单一的处理器，或者在单个封装或主板多个处理器（！），你可以依靠synchronzied TSC。

On newer CPUs (i7 Nehalem+ IIRC) the TSC is synchronzied across all cores and runs a constant rate. So for a single processor, or more than one processor on a single package or mainboard(!) you can rely on a synchronzied TSC.

从英特尔系统手册16.12.1

From the Intel System Manual 16.12.1

在新的处理器的时间戳计数器可以支持增强，
  被称为不变TSC。为不变TSC处理器支持
  通过CPUID.80000007H表示：EDX [8]。不变TSC将在运行
  恒定的速率在所有ACPI P-，C-。和T-状态。这是在
  建筑行为的向前发展。

The time stamp counter in newer processors may support an enhancement, referred to as invariant TSC. Processors support for invariant TSC is indicated by CPUID.80000007H:EDX[8]. The invariant TSC will run at a constant rate in all ACPI P-, C-. and T-states. This is the architectural behavior moving forward.

在你不能依赖于任何恒定的速度或synchronziation较老的处理器。

On older processors you can not rely on either constant rate or synchronziation.

编辑：至少在多个处理器在单个封装或主板上的不变的TSC是同步的。该TSC复位在/重置为零，然后在每个处理器上以恒定的速度向前蜱，无漂移。的/ RESET信号被保证在每个处理器在同一时间到达。

At least on multiple processors in a single package or mainboard the invariant TSC is synchronized. The TSC is reset to zero at a /RESET and then ticks onward at a constant rate on each processor, without drift. The /RESET signal is guaranteed to arrive at each processor at the same time.

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