ARM:是“STMDB SP！，{R0-R8}"(又名 PUSH {R0-R8})原子操作? [英] ARM: Is "STMDB SP!, {R0-R8}" (aka PUSH {R0-R8}) an atomic operation?

问题描述

我想知道 STMDB SP!, {R0-R8} 是否是 ARM(v7) 中的原子操作，因为它对我来说看起来很复杂.例如，CPU 在中间"某处被中断并且已经将 R5-R8 存储在堆栈中并且 SP 现在是 SP_old - 16 并且在处理中断后处理器继续使用 R0-R4 是否有可能?谢谢.

I wonder if STMDB SP!, {R0-R8} is an atomic operation in ARM(v7), because it looks quite complex to me. So is it for example possible, that the CPU is interrupted somewhere "in the middle" and has already stored R5-R8 on the stack and the SP is now SP_old - 16 and after handling the interrupt the processor continues with R0-R4? Thanks.

推荐答案

为了澄清这里稍微混乱的答案组合，首先；v7-A¹:

To clarify upon the slightly confusing mix of answers here, first up; v7-A¹:

在标准配置中唯一可以中断多路访问指令的例外是同步数据中止，因此它们在中断方面实际上是原子的(尽管 不是内存访问).

In the standard configuration the only exception that can interrupt a multiple access instruction is a synchronous data abort, so they are effectively atomic in terms of interrupts (though not in terms of memory accesses).

这是不正确的，但是，如果低延迟中断配置受支持并已启用.在这里，IRQ、FIQ 和异步中止也可以中断指令.在此引用 v7-A ARM ARM:

This is not true, however, if the low-latency interrupt configuration is supported and has been enabled. Here IRQs, FIQs and asynchronous aborts can also interrupt the instruction. To quote the v7-A ARM ARM on this:

ARM 弃用任何软件依赖的行为，即在访问普通内存的单个加载或存储指令生成的一系列内存事务中不会发生中断或异步中止.

ARM deprecates any software reliance on the behavior that an interrupt or asynchronous abort cannot occur in a sequence of memory transactions generated by a single load or store instruction that accesses Normal memory.

注意

显示这种依赖的一个特殊情况是从内存中加载堆栈指针的加载倍数.在 LDM 期间发生中断的实现中，这可能会破坏堆栈指针.

A particular case that has shown this reliance is load multiples that load the stack pointer from memory. In an implementation where an interrupt is taken during the LDM, this can corrupt the stack pointer.

以这种方式中断的指令将被放弃，如果返回，则从头开始执行(因此对于存储低地址可能会看到两次写入).

An instruction interrupted this way will be abandoned and, if returned to, execution restarted form the beginning (thus for stores the lower addresses may see two writes).

其次是 v7-M²，带有古怪的异常模型:

Secondly v7-M², with its wacky exception model:

这里每天都是低延迟的.在多个访问指令期间总是可以采取异常，但架构允许(在某些条件下)根据问题中的建议从中断点继续执行.放弃并重新启动行为也被允许作为替代方法，并且是不可继续指令/异常组合的唯一选择.

Here it's low-latency all day every day. Exceptions can always be taken during multiple access instructions, but the architecture allows (in certain conditions) for continuing execution from the point of interruption as per the suggestion in the question. Abandon-and-restart behaviour is also permitted as an alternative, and is the only option for non-continuable instruction/exception combinations.

[1] ARMv7-A ARM (DDI0406C.b)

[2] ARMv7 的 B1.5.10 部分-M ARM (DDI0403D)

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