英特尔64和IA-32 |原子操作，包括获取/释放语义 [英] Intel 64 and IA-32 | Atomic operations including acquire / release semantic

问题描述

据英特尔64和IA-32架构软件开发人员手册锁定信号preFIX确保处理器具有独占使用任何共享内存，而信号断言。这可以是一个在总线或高速缓存锁的形式。

According to the Intel 64 and IA-32 Architectures Software Developer's Manual the LOCK Signal Prefix "ensures that the processor has exclusive use of any shared memory while the signal is asserted". That can be a in the form of a bus or cache lock.

但是 - 这就是我要问这个问题的原因 - 它不是我清楚，如果这个preFIX还提供任何记忆障碍

But - and that's the reason I'm asking this question - it isn't clear to me, if this Prefix also provides any memory-barrier.

我在一个多处理器环境NASM显影和需要实现具有可选获取原子操作和/或释放的语义。

I'm developing with NASM in a multi-processor environment and need to implement atomic operations with optional acquire and/or release semantics.

所以，我需要使用MFENCE，SFENCE和LFENCE指令或将本是多余的？

So, do I need to use the MFENCE, SFENCE and LFENCE instructions or would this be redundant?

推荐答案

没有，就没有必要使用说明 MFENCE，SFENCE和LFENCE 有关与锁定 preFIX。

No, there is no need to use instructions MFENCE, SFENCE and LFENCE in relation with LOCK prefix.

MFENCE，在所有CPU内核的内存SFENCE和LFENCE 指令担保的知名度。在实例中的 MOV 指令不能用锁定 preFIX使用，所以可以肯定的是结果内存此举是为所有的CPU内核可见，我们必须确保CPU刷新缓存RAM和我们围栏指令到达。

MFENCE, SFENCE and LFENCE instruction guarantee visibility of memory in all CPU cores. On instance the MOV instruction can't be used with LOCK prefix, so to be sure that result of memory move is visible to all CPU cores we must be sure that CPU cache is flushed to RAM and that we reach with fence instructions.

编辑：更多关于英特尔手动锁定原子操作：

more about locked atomic operations from Intel manual:

锁定原子操作

32位
  IA-32处理器支持原子锁
  在系统位置的操作
  记忆。这些操作通常是
  用于管理共享数据结构
  （例如信号量，段
  描述符，系统段，或页
  表），其中两个或更多个
  处理器可以同时尝试
  修改相同的字段或标志。该
  处理器使用了三个相互依存
  实施机制锁定
  原子操作：

The 32-bit IA-32 processors support locked atomic operations on locations in system memory. These operations are typically used to manage shared data structures (such as semaphores, segment descriptors, system segments, or page tables) in which two or more processors may try simultaneously to modify the same field or flag. The processor uses three interdependent mechanisms for carrying out locked atomic operations:

•保证原子操作

•总线锁定，使用LOCK＃信号和LOCK指令preFIX

• Bus locking, using the LOCK# signal and the LOCK instruction prefix

•即确保原子操作可以在高速缓存的数据结构（缓存锁）来进行高速缓存一致性协议;这个机制是在奔腾4 present，英特尔至强和P6系列处理器

• Cache coherency protocols that insure that atomic operations can be carried out on cached data structures (cache lock); this mechanism is present in the Pentium 4, Intel Xeon, and P6 family processors

这些机制相互依存
  通过以下方式。某些基本
  内存交易（如阅读
  或写入在系统存储器中的字节）
  始终保证被处理
  原子。也就是说，一旦启动，
  处理器保证了
  操作前完成
  另一个处理器或总线代理
  允许访问的存储位置。
  该处理器还支持总线
  锁定执行选择的存储
  操作（诸如
  读 - 修改 - 写的操作
  的存储器共享区域），通常
  需要被原子处理，但
  不自动这样处理的。
  由于经常使用的内存
  地点通常缓存在一个
  处理器的L1或L2高速缓存，原子
  操作可以经常进行
  内部而没有一个处理器的高速缓存
  断言总线锁定。在这里，
  处理器的高速缓存一致性协议
  保证是其他处理器
  缓存相同的存储器位置
  管理得当而原子
  操作上进行缓存
  内存位置。

These mechanisms are interdependent in the following ways. Certain basic memory transactions (such as reading or writing a byte in system memory) are always guaranteed to be handled atomically. That is, once started, the processor guarantees that the operation will be completed before another processor or bus agent is allowed access to the memory location. The processor also supports bus locking for performing selected memory operations (such as a read-modify-write operation in a shared area of memory) that typically need to be handled atomically, but are not automatically handled this way. Because frequently used memory locations are often cached in a processor’s L1 or L2 caches, atomic operations can often be carried out inside a processor’s caches without asserting the bus lock. Here the processor’s cache coherency protocols insure that other processors that are caching the same memory locations are managed properly while atomic operations are performed on cached memory locations.

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