为什么＆QUOT; DIV＆EDX QUOT;在MASM总是生成处理器异常？ [英] Why "DIV EDX" in MASM always generates processor exception?

问题描述

我有关于信息学上学期我的计算机体系结构考试这个问题：
的为什么MASM'DIV EDX总是生成处理器异常？的结果
产生异常机制是什么？

I've got that question on my Computer Architecture Exam on Informatics last semester : "Why 'DIV EDX' in MASM always generates processor exception?"
What is the mechanism which generates exception?

推荐答案

当你做1个操作数师的x86处理器，EDX：EAX（64位）是第一个操作数（32位）划分。结果存储在EAX中（32位）。

When you do 1-operand division on x86 CPUs, EDX:EAX (64 bit) is divided by the 1st operand (32 bit). The result is stored in EAX (32 bit).

所以，当你通过除以EDX：EAX由EDX，你实际上得到的是（EDX * 0x100000000 + EAX）/ EDX，其结果总是高于0x100000000和不适合的目标寄存器或除数为零。在这两种情况下出现鸿沟例外。

So when you divide by EDX:EAX by EDX, what you essentially get is (EDX * 0x100000000 + EAX) / EDX, which result is always above 0x100000000 and does not fit into the target register or the divisor is zero. In both cases a divide exception occurs.

又见<一个href=\"https://web.archive.org/web/20120606081847/http://siyobik.info.gf/main/reference/instruction/DIV\"相对=nofollow>此页面（从英特尔开发者手册）。

See also this page (from the Intel developer manuals).

请注意，这不是特定于汇编（MASM），但在这种情况下，平台

Note that this is not specific to the assembler (MASM), but to the platform in this case.

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