如何内存围栏工作？ [英] How do memory fences work?

问题描述

我需要了解在多核机器内存栅栏。说我有这个code

核心1

  MOV [_x]，1; MOV R1，[_y]
 

的Core 2

  MOV [_y]，1; MOV R2，[_x]
 

现在无记忆栅栏意想不到的结果，将会是既R1和R2可以执行之后为0。在我看来，对付这个问题，我们应该把存储栅栏两个codeS，因为把它只有一个仍然不能解决问题。喜欢的东西如下...

核心1

  MOV [_x]，1; memory_fence; MOV R1，[_y]
 

的Core 2

  MOV [_y]，1; memory_fence; MOV R2，[_x]
 

我的理解是正确的还是我还是失去了一些东西？假设该架构86。此外，有人可以告诉我怎么把内存栅栏，C ++ code？

解决方案

栅栏序列，它们围栏（负载＆放大器;存储）操作，即，没有任何其他操作可以开始直到围栏被执行，但栅栏不会执行到所有preceding操作完成。引用英特尔使这多一点的precise（从MFENCE指令采取3-628页，第2A，英特尔的指令参考。）的含义是：

  

此序列化操作，保证每一个加载和存储
  指令，该指令precedes程序顺序MFENCE指令
  任何负载或存储指令之前变得全局可见的
  遵循MFENCE instruction.1 ​​

  
  

  
1. 负载指令被认为是成为全局可见时
     要装入其目的地寄存器中的值被确定。

  

在使用C ++围栏是棘手的（C ++ 11可能有围栏语义的地方，也许别人对这些信息），因为它是平台和编译器相关的。对于使用MSVC或ICC x86上，你可以使用 _mm_lfence ， _mm_sfence ＆安培; _mm_mfence 负载，存储和加载+存储击剑（请注意，其中有些是SSE2指令）。

请注意：这假定英特尔的角度来看，那就是：一是使用一个x86（32位或64位）或IA64处理器

I need to understand memory fences in multicore machines. Say I have this code

Core 1

mov [_x], 1; mov r1, [_y]    

Core 2

mov [_y], 1; mov r2, [_x]

Now the unexpected results without memory fences would be that both r1 and r2 can be 0 after execution. In my opinion, to counter that problem, we should put memory fence in both codes, as putting it to only one would still not solve the problem. Something like as follows...

Core 1

mov [_x], 1; memory_fence; mov r1, [_y]  

Core 2

mov [_y], 1; memory_fence; mov r2, [_x]

Is my understanding correct or am I still missing something? Assume the architecture is x86. Also, can someone tell me how to put memory fences in a C++ code?

解决方案

Fences serialize the operation that they fence (loads & stores), that is, no other operation may start till the fence is executed, but the fence will not execute till all preceding operations have completed. quoting intel makes the meaning of this a little more precise (taken from the MFENCE instruction, page 3-628, Vol. 2A, Intel Instruction reference):

This serializing operation guarantees that every load and store instruction that precedes the MFENCE instruction in program order becomes globally visible before any load or store instruction that follows the MFENCE instruction.1

1. A load instruction is considered to become globally visible when the value to be loaded into its destination register is determined.

Using fences in C++ is tricky (C++11 may have fence semantics somewhere, maybe someone else has info on that), as it is platform and compiler dependent. For x86 using MSVC or ICC, you can use the _mm_lfence, _mm_sfence & _mm_mfence for load, store and load + store fencing (note that some of these are SSE2 instructions).

Note: this assumes an Intel perspective, that is: one using an x86 (32 or 64 bit) or IA64 processor

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