如何让我的Makefile只重新编译更改的文件? [英] How do I make Makefile to recompile only changed files?
问题描述
我一直在挣扎了一下得到make编译只已编辑的文件。不过,我没有太多的成功和所有的文件被重新编译。有人可以解释我为什么?
我的文件是:
的main.c
a_functions.c
其中的main.c 包含的 main.h 的
和 a_functions.c 包含的 A.H 的
下面是我的makefile:
CC = GCC
CFLAGS = -Wall -I。 -C
EXEC_FILE =程序1
所有:程序a_functions.o:a_functions.c
a_functions.c:A.H
main.o中:main.c中
main.c中:main.h对象:a_functions.c的main.c
$(CC)a_functions.c的main.c $(CFLAGS)程序:a_functions.o main.o中
$(CC)a_functions.o main.o中-o $(EXEC_FILE)
更改makefile文件按建议似乎有同样的问题:
所有:程序a_functions.o:a_functions.c A.H
GCC a_functions.c -cmain.o中:main.c中main.h
GCC的main.c -c程序:a_functions.o main.o中
GCC a_functions.o main.o中-o程序1
你在谈论的具体问题 - make会重新生成程序1
(通过重新链接对象),甚至当一切都没有改变 - 在这样的规则:
程序:a_functions.o main.o中
GCC a_functions.o main.o中-o程序1
这条规则的目标是程序
,并让假定它是一个文件。但是,因为没有这样的文件,每次运行腾出时间,让认为该文件需要重建,并执行规则。我的建议是:
程序1:a_functions.o main.o中
GCC a_functions.o main.o中-o程序1
或者更好的做法是:
程序1:a_functions.o main.o中
GCC $ ^ -o $ @
或者更好的是:
$(EXEC_FILE):a_functions.o main.o中
$(CC)$ ^ -o $ @
(不要忘记更改所有
规则相匹配。)
一个其他几个要点:
-
由于@paxdiablo指出,
a_functions.o:a_functions.c A.H
main.o中:main.c中main.h -
这是没有意义的这些对象在一起,除非事情在一个链接(大概
main.o中
)调用其他(可能是<$ C东西$ C> a_functions.o ),所以我希望看到这样的依赖关系:main.o中:A.H
所以我怀疑你有一些错位的声明。
-
您声明
对象
规则,但从来没有参考。所以,你从来没有真正使用它;制作用来%默认规则○:%.C
。我的建议是:OBJECTS = a_functions.o main.o中
$(对象):%:%.C
$(CC)$&LT; $(CFLAGS)-o $ @(在这种情况下,您可以更改
$(EXEC_FILE):a_functions.o main.o中
到$(EXEC_FILE):$(对象)
),或者只是这样的:%○:%.C
$(CC)$&LT; $(CFLAGS)-o $ @
I have been struggling a bit to get make to compile only the files that have been edited. However I didn't have much success and all the files get recompiled. Can someone explain me why?
My files are:
main.c
a_functions.c
where main.c includes main.h and a_functions.c includes a.h
Here is my makefile:
CC=gcc
CFLAGS=-Wall -I. -c
EXEC_FILE=program1
all: program
a_functions.o: a_functions.c
a_functions.c: a.h
main.o: main.c
main.c: main.h
objects: a_functions.c main.c
$(CC) a_functions.c main.c $(CFLAGS)
program: a_functions.o main.o
$(CC) a_functions.o main.o -o $(EXEC_FILE)
Changing the makefile as per suggestions seems to have the same problem::
all: program
a_functions.o: a_functions.c a.h
gcc a_functions.c -c
main.o: main.c main.h
gcc main.c -c
program: a_functions.o main.o
gcc a_functions.o main.o -o program1
The specific problem you're talking about -- Make rebuilds program1
(by relinking the objects) even when nothing has changed -- is in this rule:
program: a_functions.o main.o
gcc a_functions.o main.o -o program1
The target of this rule is program
, and Make assumes that it is a file. But since there is no such file, every time you run Make, Make thinks that this file needs to be rebuilt, and executes the rule. I suggest this:
program1: a_functions.o main.o
gcc a_functions.o main.o -o program1
Or better, this:
program1: a_functions.o main.o
gcc $^ -o $@
Or better still this:
$(EXEC_FILE): a_functions.o main.o
$(CC) $^ -o $@
(And don't forget to change the all
rule to match.)
A few other points:
As @paxdiablo pointed out,
a_functions.o: a_functions.c a.h main.o: main.c main.h
It doesn't make sense to link these objects together unless something in one (probably
main.o
) calls something in the other (probablya_functions.o
), so I would expect to see a dependency like this:main.o: a.h
So I suspect that you have some misplaced declarations.
You declare an
objects
rule, but never refer to it. So you never actually use it; Make uses the default rule for%.o: %.c
. I suggest this:OBJECTS = a_functions.o main.o $(OBJECTS): %: %.c $(CC) $< $(CFLAGS) -o $@
(In which case you can change
$(EXEC_FILE): a_functions.o main.o
to$(EXEC_FILE): $(OBJECTS)
.) Or just this:%.o: %.c $(CC) $< $(CFLAGS) -o $@
这篇关于如何让我的Makefile只重新编译更改的文件?的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!