在Makefile文件GCC的C程序,什么是.d文件,也什么是通配符? [英] In Makefiles GCC C programs, What are .d files and also what is a wildcard.?
问题描述
在Makefile文件GCC的C程序,什么是.d文件,也什么是通配符?
In Makefiles GCC C programs, What are .d files and also what is a wildcard.?
RGDS,
推荐答案
这些 *。ð
文件通常(和公正的传统)的制作
依赖关系(但也许,和不可能, D-语言源$ C $ C)。
These *.d
files usually (and just conventionally) are make
dependencies (but perhaps, and unlikely, D-language source code).
借助 GCC编译器知道 -M
(以及相关的) preprocessor选项,它要求制作
来....
The GCC compiler knows about -M
(and related) preprocessor option, which asks make
to ....
而不是输出preprocessing,输出适合于描述化妆的主要源文件的依赖关系规则的结果。
Instead of outputting the result of preprocessing, output a rule suitable for make describing the dependencies of the main source file.
通过几个不错的帮助的Makefile
技巧,你可以写一个的Makefile
自动处理依赖关系,例如事情像
With the help of a few good Makefile
tricks, you could write a Makefile
automatically dealing with dependencies, e.g. with things like
## dependencies of foo.c
foo.d: foo.c
$(COMPILE.c) -M $^ -o $@
## include them
-include foo.d
关于 $(通配符的* .c)
,阅读的 GNU使文档,节上的文件名功能的。因此, $(通配符的* .c)
是的通配的 *。ç
按制作
它扩展到结尾的文件列表 .C
;你可以使用例如它定义一个制作
变量: SOURCE_FILES = $(通配符的* .c)
等
About $(wildcard *.c)
, read the GNU make documentation, section on file name functions. So $(wildcard *.c)
is globbing the *.c
by make
expanding it into the list of files ending with .c
; you could use it e.g. to define a make
variable: SOURCE_FILES= $(wildcard *.c)
, etc.
不要忘了尝试使-p
了解所有由GNU 制作
已知良好的内置规则。 ...使用使--trace
或 重拍
-x
对于调试的Makefile
-s
Don't forget to try make -p
to understand all the good builtin rules known by GNU make
.... Use make --trace
or remake
-x
for debugging your Makefile
-s.
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