如果我们将内存标记为WC（写组合），那么我们自动有任何一致性吗？ [英] If we marked memory as WC(Write Combined), then do we have any consistency automatically?

问题描述

我们知道在x86架构上自动提供获取 - 发布一致性 - 即所有操作自动排序，没有任何栅栏，排除第一存储和下一个加载操作。 （如第34页的Herb Sutter所述： https ：//onedrive.live.com/view.aspx？resid = 4E86B0CF20EF15AD！24884& app = WordPdf& authkey =！AMtj_EflYn2507c ）

如果我们 MFENCE（LFENCE + SFENCE）之间，则无法重新排序商店，而且无法重新排序，即我们提供了连续一致性。

但是如果我们将内存标记为 WC（写组合），那么我们是否有任何一致性自动没有任何栅栏，可能是获取释放？

或者如果我们对WC-memory使用 SSE 指令，那么我们没有任何一致性，如果我们使用简单的 MOV 指令与WC-memory，那么我们有获取 - 发布的一致性，不是吗？

解决方案

=http://stackoverflow.com/questions/13297178/how-mtrr-registers-implemented>如何实施MTRR寄存器？

存储到WC存储器：WC存储器类型非常适合具有以下特性的存储器区域（例如，视频帧缓冲器）：
1.处理器不从WC存储器高速缓存。
2.允许从WC存储器推测执行加载。
3.存储到WC存储器的存储在处理器的写组合缓冲器（WCB）中。
4.每个WCB可以容纳一行（64字节的数据）。
5.由于存储被执行到一行WC存储器空间，所以字节被累积在被分配用于记录对该存储器空间行的写入的WCB中。
6.对WCB中某个位置的后续存储可以覆盖由该位置的较早存储存储在该位置的字节。换句话说，对同一位置的多次写入将被折叠，以便位置反映写入该位置的最后一个数据字节。
7.当WCB最终通过FSB转储到外部存储器时，数据不必以先前的编程式存储被执行的相同顺序写入存储器。被写入的设备必须容忍这种类型的行为（即，它必须正确地运行）。有关详细信息，请参阅第1081页的WCB FSB事务。

我认为WC存储器没有自动一致性，因为对内存的最终写入以与之前执行的程序化存储相同的顺序写入内存。

As we know on x86 architecture the acquire-release consistency provided automatically - i.e. all operations automatically ordered without any fences, exclude first store and next load operations. (As said Herb Sutter on page 34: https://onedrive.live.com/view.aspx?resid=4E86B0CF20EF15AD!24884&app=WordPdf&authkey=!AMtj_EflYn2507c )

If we put MFENCE(LFENCE+SFENCE) between them, then store can't be reordered, and load can't be reordered - i.e. we provided sequential consistency.

But if we marked memory as WC(Write Combined), then do we have any consistency automatically without any fences, may be acquire-release?

Or if we use SSE instructions with WC-memory, then we have not any consistency, and if we use simple MOV instructions with WC-memory, then we have acquire-release consistency, isn't it?

解决方案

As stated here: How MTRR registers implemented?

Stores to WC Memory: The WC memory type is well-suited to an area of memory (e.g., the video frame buffer) that has the following characteristics: 1. The processor does not cache from WC memory. 2. Speculative execution of loads from WC memory is permitted. 3. Stores to WC memory are deposited in the processor's Write Combining Buffers (WCBs). 4. Each WCB can hold one line (64 bytes of data). 5. As stores are performed to a line of WC memory space, the bytes are accumulated in the WCB assigned to record writes to that line of memory space. 6. A subsequent store to a location in a WCB can overwrite a byte that was deposited in that location by an earlier store to that location. In other words, multiple writes to the same location are collapsed so that the location reflects the last data byte written to that location. 7. When the WCBs are ultimately dumped to external memory over the FSB, data is not necessarily written to memory in the same order in which the earlier programmatic stores were executed. The device being written to must tolerate this type of behavior (i.e., it must function correctly). See "WCB FSB Transactions" on page 1080 for more information.

I believe there is no "automatic consistency" for WC memory since the final writes to memory are "not necessarily written to memory in the same order in which the earlier programmatic stores were executed".

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