缓存一致性-MESI协议 [英] Cache coherence- MESI protocol

问题描述

在采用MESI协议(具有l1和l2包含性)的高速缓存中是否可能存在其中l2可以将无效指令发送到l1中已经无效的行的情况.

Can there be a case in a cache employing a MESI protocol (has l1 and l2 inclusivity employed) where l2 can send an invalid instruction to an already invalid line in l1.

推荐答案

在某些情况下，L2根本不知道L1是否有线路，因为允许L1静默丢弃它.

There could be a scenario where the L2 simply does not know if the L1 has the line, because the L1 is allowed to silently drop it.

实际上，如果包含L2，则从L1撤消未修改的线路(容量逐出)时，几乎没有任何理由浪费带宽，因为L2已经具有副本并且没有变化.因此，很可能L2中的许多行在从L1中逐出后仍会停留很长时间.当L2最终到达时(后来，由于更大)，从L2驱逐将不得不发回监听以强制执行包容性，因为无法确定该行是否仍在L1中.

In fact, if the L2 is inclusive, there's hardly any reason to waste bandwidth when evicting a non-modified line from the L1 (capacity eviction), because the L2 already has a copy and there's no change. It is therefore likely that many lines in the L2 are still there long after they were evicted from the L1. An eviction from the L2 when it finally arrives (later, since it's bigger) would have to send back a snoop to enforce inclusiveness, because it can't be sure if the line is still in the L1 or not.

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