不同级别的缓存(即L1，L2和L3)之间的缓存一致性(MESI协议) [英] Cache coherency(MESI protocol) between different levels of cache namely L1, L2 and L3

问题描述

这是关于 cache 的不同层的缓存一致性协议.我对 L1 的理解(X86_64)是，它仅由一个内核拥有，并且 L2 在2个内核之间，而对于所有内核， L3 在CPU插槽中.我已经阅读了 MESI 协议的功能，有关存储缓冲区，使队列无效，使消息无效等.我的疑问是，这是适用于 L1 MESI 仅>，或者它也适用于 L2 和 L3 .还是在 L2 和 L3 之间有不同的同步缓存.

This is about cache coherency protocol across different layers of cache. My understanding(X86_64) about L1 is that, it is owned exclusively by a core and L2 is between 2 cores and L3 for all the cores in a CPU socket. I have read the MESI protocol functioning, about store buffers, invalidate queues, invalidate messages etc. My doubt here is that is the MESI applicable for L1 only or it is applicable for L2 and L3 as well. Or is there a different cache synchronizing between for L2 and L3 .

推荐答案

缓存级别的数量，相对于系统中其他处理器或内核的每个级别的组织方式以及在每个缓存中实现的一致性协议的定义如下:核心微体系结构，非核心微体系结构，以及在某些情况下相关的启动时配置选项.这些设计方面因供应商和处理器的一代以及同一代中的型号而异.即使您只考虑过去几年中发布的处理器，也会有很多不同的设计.

The number of cache levels, how each level is organized with respect to other processors or cores in the system, and the coherence protocol implemented in each cache is defined by the core microarchitecture, the uncore microarchitecture, and, in some cases, relevant boot-time configuration options. These design aspects vary by vendor and processor generation and models within the same generation. There a lot of different designs even if you just consider the processors released in the past few years.

Intel和AMD始终清楚地记录缓存层次结构的组织.但是，一致性协议并不总是清楚地记录在案.您不会在任何官方文档中找到直接告诉您所有缓存使用协议的章节.一些硬件性能事件名称暗示了事件适用的高速缓存中使用的一致性协议.

The organization of the cache hierarchy is always clearly documented by Intel and AMD. However, the coherence protocols are not always clearly documented. You won't find a section in any official document that directly tells you all the protocols that caches use. Some hardware performance event names allude to what coherence protocol is used in the cache to which the events apply.

指令高速缓存(L1I)始终使用SI协议，因为在填充点和无效点之间永远不会修改行.因此，一个条目可以处于S或I状态.M和E状态仅相关，并且缓存支持修改现有行.

The instruction cache (L1I) always uses the SI protocol because a line is never modified between the point of fill and the point of invalidation. So an entry can either be in the S or I state. The M and E states are only relevant and the cache supports modifying an existing line.

某些微体系结构具有仅支持直写写命中策略的缓存.例如，AMD Bulldozer中的L1D是直写式缓存.在直写式高速缓存中，M状态没有意义.这意味着L1D使用SI或ESI.SI的可能性更大，因为每个条目只需要一个状态位即可.

Some microarchitectures have caches that only support the write-through write hit policy. For example, the L1D in the AMD Bulldozer is a write-through cache. The M state doesn't make sense in a write-through cache. This means that the L1D either uses SI or ESI. SI is more likely because it requires only a single bit of state per entry.

英特尔处理器几乎始终在所有数据和统一缓存中支持回写策略.具有两级缓存的老式英特尔处理器(90年代和2000年代初)将L1D和L2使用MESI.具有三级缓存的英特尔处理器也将MESI用于L1D和L2.四个状态可用的事实并不一定意味着所有状态都在使用中.物理地址位于具有直写(WT)内存类型的区域内的高速缓存行不使用M状态.(很有可能类型从WB更改为WT，因此第一个WT接入可能会打入M.)因此WT线路的有效协议是ESI或SI.

Intel processors almost always support the write-back policy in all data and unified caches. Old Intel processors (90s and early 2000s) with two levels of caches use MESI for the L1D and L2. Intel processors with three levels of caches also uses MESI for the L1D and L2. The fact that four states are available doesn't necessarily mean that all are being used. A cache line whose physical address falls within a region with the write-through (WT) memory type doesn't use the M state. (It's possible that the type changed from WB to WT, so the first WT access could hit in M.) So the effective protocol for a WT line is ESI or SI.

从Nehalem-EX开始的Intel处理器中的L3高速缓存使用MESIF协议，并为整个NUMA节点提供包含目录(在命中时使用).Nehalem-EX还使用内存中的2状态目录来跟踪打包的IOH拥有哪些行.内存目录协议在Westmere-EX中发生了变化，然后在Xeon E5中发生了变化，在Xeon E5/E7 v2中发生了变化，在Xeon E5/E7 v3中发生了变化.这些处理器在L3缺失场景中还具有多种折衷方案，支持多种一致性协议.

The L3 caches in Intel processors starting with Nehalem-EX uses the MESIF protocol with an inclusive directory (used on a hit) for the entire NUMA node. Nehalem-EX also employs an in-memory 2-state directory to track which lines are owned by the off-package IOH. The in-memory directory protocol changed in Westmere-EX, and then changed again in the Xeon E5, and again in the Xeon E5/E7 v2, and again in the Xeon E5/E7 v3. These processors also support multiple coherence protocols in the L3-miss scenario with different tradeoffs.

我不确定还要说些什么来回答您的问题.我猜您可能会说MESI或多或少适用于L2和L3.

I'm not sure what else to say to answer your question. I guess you could say that MESI is more or less applicable to the L2 and L3.

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