如何接收L1，L2&在x86中使用CPUID指令的L3缓存大小 [英] How to receive L1, L2 & L3 cache size using CPUID instruction in x86

问题描述

我在准备汇编程序x86项目时遇到问题，该问题是编写一个程序以获取L1数据，L1代码，L2和L3高速缓存大小。

I encountered a problem during preparing an assembler x86 project which subject is to write a program getting L1 data, L1 code, L2 and L3 cache size.

我试图在Intel Documentation&在互联网上，但我失败了。

I tried to find something in Intel Documentation & in the Internet but I failed.

主要问题是：对于AMD处理器，只需将EAX寄存器设置为80000005h& 80000006h值，并从ECX和EDX寄存器获取所需的数据，但是对于Intel，我只能为L2获取此信息。

THE MAIN PROBLEM IS: In case of AMD processors it is just to set EAX register to 80000005h & 80000006h values and get desired data from ECX and EDX registers but in case of Intel I can obtain this information only for L2.

我应该怎么做才能获得L1&英特尔处理器的三级缓存大小？

What should I do to get L1 & L3 cache size for Intel processors ?

推荐答案

Marat Dukhan基本上给了您正确的答案。对于较新的Intel处理器（即过去5-6年内生产的处理器），最好的解决方案是枚举cpuid叶子4，这意味着您多次调用cpuid，首先使用EAX = 4和ECX = 0，然后使用EAX = 4，ECX = 1，依此类推。这不仅会返回有关缓存大小和类型的信息，还会告诉您这些缓存如何连接到CPU内核和超线程/ SMT单元。在 https：中给出算法和示例代码： //software.intel.com/zh-cn/articles/intel-64-architecture-processor-topology-enumeration/ ，更具体地说，在高速缓存拓扑枚举部分中。

Marat Dukhan basically gave you the right answer. For newer Intel processors, meaning those made in the last 5-6 years, the best solution is to enumerate over the cpuid leaf 4, meaning you call cpuid a few times, first with EAX=4 and ECX=0, then with EAX=4 and ECX=1 and so forth. This will return info not only on the cache sizes and types but also tell you how these caches are connected to the CPU cores and hyperthreading/SMT units. The algorithm and sample code is given at https://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/ , more specifically in the section titled "Cache Topology Enumeration".

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