强制 L1 缓存未命中 [英] Force to L1 cache miss

问题描述

我想强制我的程序每次(或几乎每次)都错过缓存 L1.

I would like to force my program to miss cache L1 every time ( or nearly every time).

所以，我的 IvyBridge 有 32 KB L1 缓存，它是 8 路.因此，每组包含 8 行，每行有 64 个字节.要设置的地址映射的前 6 位，行中偏移的最后 7 位映射，其他位确定标记.

So, my IvyBridge has 32 KB L1 cache and it is 8-way. Therefore, every set contains 8 lines and every line has 64 bytes. First 6 bits of address map to set, 7 last bit map to offset in line, and others bits determine a tag.

如何错过缓存?我应该使用来自同一组的 8 个(每组有 8 行)不同的加载操作吗?

How to miss cache? Should I use 8 ( every set has 8 lines) different load operation from the same set?

推荐答案

是的，您走对了.使用全部位于同一组中的地址可以让您以最少的不同地址测试 L1 缓存未命中.

Yeah, you're on the right track. Using addresses that will all go in the same set will let you test L1 cache misses with the fewest different addresses.

然而，8个不同的地址显然是不够的，因为它们都可以放在一个集合中.最好的办法是将它加倍或四倍，这样 LRU 驱逐算法就有足够的机会在你回来之前驱逐它.

However, 8 different addresses is obviously not enough, since they can all fit into one set. Your best bet is to double or quadruple it, to give the LRU eviction algorithm plenty of chances to evict a line before you come back to it.

不过，如果您在太多页面上使用太多不同地址，请注意 TLB 未命中.2MB 大页面可以帮上忙.

Beware of TLB misses, though, if you use too many different addresses on too many pages. 2MB hugepages can help here.

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