L1缓存的延迟访问时间 [英] Latency access times for L1 cache

问题描述

在此网络链接上:

http://www.7-cpu.com/cpu/IvyBridge.html

它说Ivy Bridge L1缓存访问的延迟是:

it says the latency for Ivy Bridge L1 cache access is:

• L1数据缓存延迟= 4个周期，用于通过指针进行简单访问
• L1数据高速缓存延迟= 5个周期，用于使用复杂地址计算(size_t n，* p; n = p [n])进行访问.

• L1 Data Cache Latency = 4 cycles for simple access via pointer
• L1 Data Cache Latency = 5 cycles for access with complex address calculation (size_t n, *p; n = p[n]).

不是指针"simple"，而是指针大小是否与单词大小相同?那么，如果指针是32位的，并且它是32位的操作系统，那么这将是简单的"，否则将花费复杂的"延迟吗?

Instead of "simple", did they mean if the pointer size is the same as the word size? So if the pointer is 32-bit and its a 32-bit OS then this would be "simple", otherwise it would cost the "complex" latency?

我只是不太理解他们对这两种潜伏期差异的解释.

I just don't quite understand their explanation for the difference in the two latencies.

推荐答案

完整的x86有效地址看起来像displacement + base + index * scale(其中displacement是常量，base和index是寄存器，而scale是1、2、4或8).

The full x86 effective address looks like displacement + base + index * scale (where displacement is a constant, base and index are registers, and scale is 1, 2, 4 or 8).

听起来，如果仅出现displacement(或者可能还包括base术语)，他们称地址简单，而具有index * scale肯定属于复杂类别.

It sounds like they call an address simple if only the displacement is present (or maybe additionally the base term), while having index * scale would certainly fall under the complex category.

更新:确实，英特尔优化手册中有以下声明(不过，是针对Sandy Bridge的):常见的加载延迟是五个周期.使用简单的寻址模式时，基加偏移量为 小于2048时，加载延迟可以为四个周期.另请参阅表2-12. 寻址模式对负载延迟的影响.

Update: Indeed, the intel optimization manual has this statement (for Sandy Bridge, though): The common load latency is five cycles. When using a simple addressing mode, base plus offset that is smaller than 2048, the load latency can be four cycles. See also Table 2-12. Effect of Addressing Modes on Load Latency.

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