关于超线程中L1缓存的自适应模式 [英] About Adaptive Mode for L1 Cache in Hyper-threading

问题描述

我是一名学生，最近正在做一些有关超线程的研究.我对该功能感到有点困惑-L1数据缓存上下文模式.

I'm a student doing some research on Hyper-threading recently. I'm a little confused about the feature - L1 Data Cache Context Mode.

在

In the architecture optimization manual, it was described that L1 cache can operate in two modes:

• 第一级缓存可以根据上下文ID位在两种模式下运行:

• The first level cache can operate in two modes depending on a context-ID bit:

1. 共享模式:L1数据缓存由两个逻辑处理器完全共享.

1. Shared mode: The L1 data cache is fully shared by two logical processors.

自适应模式:在自适应模式下，使用页面目录的内存访问在共享L1数据高速缓存的逻辑处理器之间被映射为相同.

Adaptive mode: In adaptive mode, memory accesses using the page directory is mapped identically across logical processors sharing the L1 data cache.

但是，我很好奇根据描述如何在自适应模式下对缓存进行分区.

However, I am curious about how cache get partitioned in the adaptive mode according to the description.

推荐答案

在Intel arch上， L1 Context ID 的值为1表示可以将L1数据缓存模式设置为自适应模式或共享模式，而值0表示不支持此功能.有关详细信息，请检查 IA32_MISC_ENABLE MSR位24 (L1数据高速缓存上下文模式)的定义.

On Intel arch, a value of 1 of L1 Context ID indicates the L1 data cache mode can be set to either adaptive mode or shared mode, while a value of 0 indicates this feature is not supported. Check the definition of IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for details.

根据

According to Intel® 64 and IA-32 Architectures Developer's Manual: Vol. 3A (Chapter 11/Cache Control), which I quote below:

• 共享模式

在共享模式下，逻辑处理器之间竞争性地共享L1数据高速缓存.即使逻辑处理器使用相同的CR3寄存器和分页模式，也是如此.在共享模式下，可以对L1数据高速缓存中的线性地址进行别名处理，这意味着高速缓存中的一个线性地址可以指向不同的物理位置.解决混叠的机制可能导致抖动.因此，对于支持Intel超线程技术的基于Intel NetBurst微体系结构的处理器，IA32_MISC_ENABLE [bit 24] = 0是首选配置.

In shared mode, the L1 data cache is competitively shared between logical processors. This is true even if the logical processors use identical CR3 registers and paging modes. In shared mode, linear addresses in the L1 data cache can be aliased, meaning that one linear address in the cache can point to different physical locations. The mechanism for resolving aliasing can lead to thrashing. For this reason, IA32_MISC_ENABLE[bit 24] = 0 is the preferred configuration for processors based on the Intel NetBurst microarchitecture that support Intel Hyper-Threading Technology.

• 自适应模式

自适应模式有助于逻辑处理器之间的L1数据高速缓存共享.在自适应模式下运行时，如果满足以下条件，则在同一内核中的逻辑处理器之间共享L1数据缓存:

Adaptive mode facilitates L1 data cache sharing between logical processors. When running in adaptive mode, the L1 data cache is shared across logical processors in the same core if:

•共享高速缓存的逻辑处理器的CR3控制寄存器是相同的.

• CR3 control registers for logical processors sharing the cache are identical.

•共享高速缓存的逻辑处理器使用相同的分页模式.

• The same paging mode is used by logical processors sharing the cache.

在这种情况下，整个L1数据高速缓存可用于每个逻辑处理器(而不是竞争性共享).如果共享L1数据高速缓存的逻辑处理器的CR3值不同，或者逻辑处理器使用不同的分页模式，则处理器将争用高速缓存资源.这减小了每个逻辑处理器的高速缓存的有效大小.不允许对缓存进行别名化(这可以防止数据崩溃).

In this situation, the entire L1 data cache is available to each logical processor (instead of being competitively shared). If CR3 values are different for the logical processors sharing an L1 data cache or the logical processors use different paging modes, processors compete for cache resources. This reduces the effective size of the cache for each logical processor. Aliasing of the cache is not allowed (which prevents data thrashing).

我只是猜想对L1数据缓存进行分区没有确定的方法.

I just guess there is no definite approach for partitioning the L1 data cache.

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