Makefile(自动依赖生成) [英] Makefile (Auto-Dependency Generation)
问题描述
只是为了快速的术语:
#basic makefile规则
目标:依赖项
recepie
问题:我想自动生成依赖项。
例如,我希望这样做:
我的目标的#one
file.o: file.cpp 1.h 2.h 3.h 4.h 5.h 6.h 7.h 8.h another.h lot.h evenMore.h
$(COMPILE)
进入:
#一个目标
file.o:$(GENERATE)
$(COMPILE)
我不太确定是否可以..
我所知道的:
我可以使用这个编译器标志:
g ++ -MM file.cpp
/ pre>
,它将返回正确的目标和依赖关系。
从示例中,它将返回:file.o:file.cpp 1.h 2.h 3.h 4.h 5.h 6.h 7.h 8.h另一个。 HL ots.h evenMore.h
然而,'make'不允许我明确地写shell代码规则的目标或依赖部分:(
我知道有一个'make'函数叫做 shell
但是我不能把这个插件作为依赖,并且解析魔术,因为它依赖在代表目标的宏$ @上,或至少我认为这是什么问题
我甚至尝试只是替换file.cpp依赖使用这个makefile函数,这将不起作用。
#假设要转动$ @(file.o)进入file.cpp
THE_CPP:= $(addsuffix $(。cpp),$(basename $ @))
我的目标的#one
file.o:$( THE_CPP)1.h 2.h 3.h 4.h 5.h 6.h 7.h 8.h another.h lot.h evenMore.h
$(COMPILE)
#this does不工作
所以所有ove r谷歌,似乎有两个解决方案。这两个都不完全掌握。
从GNU Make手册
所以我最终的问题是:是否可以按照我想要的方式要做到这一点,
,如果没有,可以从其中一个站点分解代码,并向我详细说明它们的工作原理。我会实现它之一,如果我必须这样做,但我厌倦了,只需将一个代码片段粘贴到我的makefile中,然后再理解它解决方案较新版本的GCC具有-M选项,可用于-MD。我简单地将-MP和-MD添加到我的项目的CPPFLAGS变量(我没有编写用于编译C ++的自定义配方),并添加了一个-include $(SRC:.cpp = .d)行。
使用-MD和-MP给出一个依赖文件,其中包含依赖关系(不必使用一些奇怪的sed)和虚拟目标(以便删除头文件不会导致错误)。
just for quick terminology:
#basic makefile rule target: dependencies recepie
The Problem: I want to generate the dependencies automatically.
For example, I am hoping to turn this:
#one of my targets file.o: file.cpp 1.h 2.h 3.h 4.h 5.h 6.h 7.h 8.h another.h lots.h evenMore.h $(COMPILE)
Into this:
#one of my targets file.o: $(GENERATE) $(COMPILE)
and I'm not too sure if it's possible..
What I do know:
I can use this compiler flag:
g++ -MM file.cpp
and it will return the proper target and dependency.
so from the example, it would return:file.o: file.cpp 1.h 2.h 3.h 4.h 5.h 6.h 7.h 8.h another.h lots.h evenMore.h
however, 'make' does NOT allow me to explicitly write shell code in the target or dependency section of a rule :(
I know there is a 'make' function called shellbut I can't quite plug this in as dependency and do parsing magic because it relies on the macro $@ which represents the target.. or at least I think that’s what the problem is
I've even tried just replacing the "file.cpp" dependency with this makefile function and that won't work either..
#it's suppose to turn the $@ (file.o) into file.cpp THE_CPP := $(addsuffix $(.cpp),$(basename $@)) #one of my targets file.o: $(THE_CPP) 1.h 2.h 3.h 4.h 5.h 6.h 7.h 8.h another.h lots.h evenMore.h $(COMPILE) #this does not work
So all over google, there appears to be two solutions. both of which I don't fully grasp.
From GNU Make ManualSome Site that says the GNU Make Manual one is out-of-date
So my ultimate question is: is it possible to do it the way I want to do it,
and if not, can somebody break down the code from one of these sites and explain to me in detail how they work. I'll implement it one of these ways if I have to, but I'm weary to just paste a chuck of code into my makefile before understanding it解决方案Newer versions of GCC have an -MP option which can be used with -MD. I simply added -MP and -MD to the CPPFLAGS variable for my project (I did not write a custom recipe for compiling C++) and added an "-include $(SRC:.cpp=.d)" line.
Using -MD and -MP gives a dependency file which includes both the dependencies (without having to use some weird sed) and dummy targets (so that deleting header files will not cause errors).
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