认识字对齐 [英] Understanding word alignment

问题描述

我明白它的意思访问内存，使得它对齐，但我不明白为什么这是必要的。例如，为什么我从一个地址访问一个字节 0X ... 1 ，但我不能从同一地址访问一个半字（两个字节）。

I understand what it means to access memory such that it is aligned but I don’t understand why this is necessary. For instance, why can I access a single byte from an address 0x…1 but I cannot access a half word (two bytes) from the same address.

此外，我明白，如果你有一个地址 A 和大小的对象取值的访问如果对齐modS = 0 。但我就是不明白这是为什么在硬件水平的重要。

Again, I understand that if you have an address A and an object of size s that the access is aligned if A mod s = 0. But I just don’t understand why this is important at the hardware level.

推荐答案

硬件是复杂的;这是一个简单的解释。的

一个典型的现代计算机可能有一个32位数据总线。这意味着任何获取该CPU需要做将获取所有32位的特定的存储器地址。由于数据总线无法获取任何比32位更小，最低的两个地址位，甚至没有使用的地址总线上，所以就好像RAM被组织成一个序列的32位的字而不是8位的字节的。

A typical modern computer might have a 32-bit data bus. This means that any fetch that the CPU needs to do will fetch all 32 bits of a particular memory address. Since the data bus can't fetch anything smaller than 32 bits, the lowest two address bits aren't even used on the address bus, so it's as if RAM is organised into a sequence of 32-bit words instead of 8-bit bytes.

在CPU做了取为一个字节，总线上的读周期将获取32位，那么CPU就会丢掉位24，装载其余8位到任何寄存器。如果CPU要取32位值，该值是不的在32位边界对齐，它有几个一般选择：

When the CPU does a fetch for a single byte, the read cycle on the bus will fetch 32 bits and then the CPU will discard 24 of those bits, loading the remaining 8 bits into whatever register. If the CPU wants to fetch a 32 bit value that is not aligned on a 32-bit boundary, it has several general choices:

• 执行在总线上两个分开的读周期加载数据字的适当的部件和将它们重
• 读取32位字，在扔地址而去的低二位确定的地址。
• 在读组装成一个32位字的字节一些意想不到的组合，可能不是你想要的那个人
• 在抛出一个异常

在不同的CPU我曾与已经采取了所有四个这些路径。在一般情况下，实现最大的兼容性是最安全的方式调整所有n位读取到n位的边界。但是，你当然可以走捷径，如果你确信你的软件将运行在某些特定的CPU家族与已知的未对齐的读取行为。即使未对齐的读取是可能的（如x86系列CPU的），他们会慢一些。

Various CPUs I have worked with have taken all four of those paths. In general, for maximum compatibility it is safest to align all n-bit reads to an n-bit boundary. However, you can certainly take shortcuts if you are sure that your software will run on some particular CPU family with known unaligned read behaviour. And even if unaligned reads are possible (such as on x86 family CPUs), they will be slower.

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