VHDL中的图像处理流水线技术 [英] Image Processing Pipelining in VHDL

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本文介绍了VHDL中的图像处理流水线技术的处理方法,对大家解决问题具有一定的参考价值,需要的朋友们下面随着小编来一起学习吧!

问题描述

我目前正在尝试用VHDL开发Sobel滤波器。我正在使用存储在BRAM中的640x480图片。该算法使用图像的3×3像素矩阵来处理每个输出像素。我的问题是我目前只知道将图像放入BRAM,其中BRAM的每个地址都包含一个像素值。这意味着我每个时钟只能读取一个像素。我的问题是我正在尝试管道数据,所以理想情况下我需要能够每个时钟获得三个像素值(图片的每一行一个),所以在我的初始延迟后,我可以加载三个新的像素值时钟并在每个时钟上获得一个输出像素。我正在寻找一种方法来做到这一点,但无法弄明白。

I am currently trying to develop a Sobel filter in VHDL. I am using a 640x480 picture that is stored in a BRAM. The algorithm uses a 3x3 matrix of pixels of the image for processing each output pixel. My problem is that I currently only know of putting an image into a BRAM where each address of the BRAM holds one pixel value. This means I can only read one pixel per clock. My problem is that I am trying to pipeline the data so I would ideally need to be able to get three pixel values (one from each row of the picture) per clock so after my initial latency, I can load in three new pixel values per clock and get an output pixel on every clock. I am looking for a way to do this but cannot figure it out.

我能想到解决这个问题的唯一方法就是将图像放在3个BRAM中。这样我就可以读取每个时钟周期3行的值。但是,没有足够的内存空间来容纳一个足够大的RAM以适应640x480图像,更不用说三个。我可以通过这种方式降低图片大小,但我真的想用我目前的640x480图像尺寸来做。

The only way I can think of to fix this is to have the image in 3 BRAMs. that way I can read in values from 3 rows per each clock cycle. However, there is not enough memory space to fit even one more RAM large enough to fit a 640x480 image let alone three. I could lower the picture size to do it this way, but I really want to do it with my current 640x480 image size.

任何帮助或指导都将不胜感激。

Any help or guidance would be greatly appreciated.

推荐答案

我几年前制作了一个sobel滤镜。为此,我写了一个在每个时钟周期给出9个像素的管道:

I made a sobel filter few years ago. To do that, i wrote a pipeline that gives 9 pixels at each clock cycle:

architecture rtl of matrix_3x3_builder_8b is
type fifo_t is array (0 to 2*IM_WIDTH + 2) of std_logic_vector(7 downto 0);
signal fifo_int : fifo_t;

begin    

    p0_build_5x5: process(rst_i,clk_i)
    begin
        if( rst_i = '1' )then
            fifo_int <= (others => (others => '0'));
        elsif( rising_edge(clk_i) )then
             if(data_valid_i = '1')then
                for i in 1 to 2*IM_WIDTH + 2 loop
                    fifo_int(i) <= fifo_int(i-1);
                end loop;           
                fifo_int(0) <= data_i;  
            end if;
        end if;
    end process p0_build_5x5;

data_o1 <= fifo_int(0*IM_WIDTH + 0);
data_o2 <= fifo_int(0*IM_WIDTH + 1);
data_o3 <= fifo_int(0*IM_WIDTH + 2);
data_o4 <= fifo_int(1*IM_WIDTH + 0);
data_o5 <= fifo_int(1*IM_WIDTH + 1);
data_o6 <= fifo_int(1*IM_WIDTH + 2);
data_o7 <= fifo_int(2*IM_WIDTH + 0);
data_o8 <= fifo_int(2*IM_WIDTH + 1);
data_o9 <= fifo_int(2*IM_WIDTH + 2);

end rtl;

在这里,您逐像素地读取图像以构建3x3矩阵。管道填​​充时间较长,但一旦完成,每个时钟脉冲都会有一个新的矩阵。

Here you read the image pixel by pixel to build your 3x3 matrix. The pipeline is longer to fill up but once completed, you have a new matrix each clock pulse.

这篇关于VHDL中的图像处理流水线技术的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!

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