如何在不使用特殊二进制格式的情况下读取VHDL / modelsim中的二进制数据 [英] How can I read binary data in VHDL/modelsim whithout using special binary formats

问题描述

我正在为以太网MAC编写VHDL测试平台。测试平台由一个包和一个组合的实体+体系结构文件组成。我想读取测试平台将从我从wireshark导出的二进制文件发送到MAC的以太网帧。

我正在用VHDL 2008编写，我正在使用Mentor Graphics Model Technology ModelSim ALTERA vcom 10.0d编译器。

I am writing a VHDL test bench for a ethernet MAC. The testbench consists of a package and an combined entity + architecture file. I want to read the ethernet frames that the testbench will send to the MAC from a binary file which I exported from wireshark.
I'm writing in VHDL 2008 and I'm using a Mentor Graphics Model Technology ModelSim ALTERA vcom 10.0d Compiler.

所有用于读取VHDL / modelsim中二进制数据的解决方案到目前为止，我发现使用特殊文件格式，其中bit_vector的1位由文件中的几位表示。我希望VHDL将二进制文件读入8位bit_vectors。

最近我到目前为止使用的是字符类型文件，我可以直接以二进制表示形式写入8位ASCII字符。

All solutions for reading binary data in VHDL/modelsim that I've found so far use special file formats where 1 bit of the bit_vector is represented by several bits in the file. I would like VHDL to read the binary file into 8 bit bit_vectors.
Closest I've gotten so far was using a character type file, where I can write 8 bit ASCII characters directly in binary representation.

推荐答案

我曾经这样做，但发现编写一个简短的脚本（用严肃的文本处理语言）来转换更有效率从任何输入到真正的VHDL文件，数据描述为合适数据类型的常量数组。

I used to do this, but have found it more productive to write a short script (in a serious text processing language) to convert from whatever input to a real VHDL file with the data described as a constant array of a suitable datatype.

这比在VHDL IMHO中进行文件解析要容易得多。

This is much easier than doing file parsing in VHDL IMHO.

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