当有负数和数组时，用verilog读写 [英] read and write in verilog when having negative numbers and array

问题描述

我现在正在读取来自txt文件的输入数据并将结果写入txt文件。

I am now doing reading input data from txt file and write the results into txt file.

然而，在模拟中运行的结果运行良好，但它无法链接回模块，即o = a + b;系统能够读取x.txt和d.txt中的值，但无法将其链接回a和b。我的错误是什么以及如何纠正它？

However the results runs in the simulation works well but it fail to link back the the conv module which is o = a+b; the system able to read the values in x.txt and d.txt but cannot link it back to a and b. What is my mistake and how to correct it?

从我发现的相同情况中，系统无法写出负十进制值，尽管它改为％ d'thin $ fwrite。任何解决方法？我应该使用$ dumpfile来获取负数作为输出吗？

And from the same cases in i found out that the system cannot write out negative decimal value although it is change to "%d\n" in $fwrite. Any method to solve that? Should i use $dumpfile to get negative number as output??

这是d.txt中的内容

Here is the content in d.txt

56
272
1
-62
75

x.txt中的内容

562
2723
14
-620
751

这是我的模块代码：

module conv (input signed[15:0]a,b,
         output signed[15:0] o);

assign o = a + b;
endmodule

我的测试平台代码：

module conv_tb();

reg clk;
reg signed [15:0]a[4:0];
reg signed [15:0]b[4:0];
wire signed [15:0]o[4:0];

integer ai,bi,oo,i;

conv U1(.a(a),.b(b),.o(o));

initial begin
    clk <= 1'b0;
    forever
    #1 clk = ~clk;
end

initial begin
   ai = $fopen("x.txt","r");
   bi = $fopen("d.txt","r");
   oo = $fopen("o.txt","w");
   #1;
   for (i = 0; i<5; i=i+1)
       a <= $fscanf(ai,"%d\n",x);
       b <= $fscanf(bi,"%d\n",d);
       #4;
       $fwrite(oo,"%d\n",o);
   end
   $fclose(ai);
   $fclose(bi);
   $fclose(oo);
   $finish;
   end
endmodule

推荐答案

使用fwrite将签名号码写入文本文件的示例：

An example for writing signed number to a text file using fwrite :

module write_signed;
integer out_file;
initial begin
   out_file = $fopen("out_file.txt","w");
   $fwrite(out_file, "%d\n", 3);
   $fwrite(out_file, "%d\n", 2);
   $fwrite(out_file, "%d\n", 1);
   $fwrite(out_file, "%d\n", 0);
   $fwrite(out_file, "%d\n", -1);
   $fwrite(out_file, "%d\n", -2);
   $fclose(out_file);
end

endmodule

生成：

      3
      2
      1
      0
     -1
     -2

这篇关于当有负数和数组时，用verilog读写的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！