Verilog 数组语法 [英] Verilog array syntax

问题描述

我是 Verilog 的新手，遇到了很多麻烦.例如，我想要一个包含 8 个单元格的数组，每个单元格的宽度为 8 位.以下不起作用:

I'm new to Verilog, and am having a lot of trouble with it. For example, I want to have an array with eight cells, each of which is 8 bits wide. The following doesn't work:

reg [7:0] transitionTable [0:7];
assign transitionTable[0] = 10;

不只是做 transitionTable[0] = 10; 或 transitionTable[0] = 8'h10; 有什么想法吗?

neither does just doing transitionTable[0] = 10; or transitionTable[0] = 8'h10; Any ideas?

(如果它不明显且不相关:我想制作一个有限状态机，并在数组中指定状态转换，因为这似乎比大规模案例切换更容易.)

(In case it is not obvious and relevant: I want to make a finite state machine, and specify the state transitions in an array, since that seems easier than a massive case switch.)

推荐答案

当使用 assign 时，您应该将数组声明为 wire 而不是 reg.

When using assign you should declare the array as a wire instead of areg.

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