Verilog阻止分配 [英] Verilog Blocking Assignment

问题描述

我对Verilog有点陌生.我知道在时钟进程中，我们应该使用非阻塞分配，而在非时钟进程中，我们应该使用阻塞分配.

I am somewhat new to Verilog. I know that in a Clock Process we should use non blocking assignments, and in a Non Clock processes, we use blocking assignments.

当我阅读别人的代码时，我遇到了这段代码.

I have came across this code, when I was reading someone else's code.

reg iowrb_int,iowrb_met;
reg iordb_int,iordb_met;
always@(*)
begin
  iowrb_int <= iowrb_met;
  iordb_int <= iordb_met;

  iowrb_met <= iowr_bar;
  iordb_met <= iord_bar;
end

我真的不确定上面的代码！我认为它没有进行任何注册，对吗?在always @(*)语句中具有非阻塞性意味着什么吗?

I am really not sure about the above code ! I don't think it is doing any registering, correct? Would it mean anything to have a non-blocking in a always@(*) statement ?

在always @(*)语句中使用阻塞与非阻塞有什么区别吗?

Is there any difference in using blocking vs non-blocking in a always@(*) statement ?

推荐答案

主要区别是:

• 阻塞分配在下一个分配之前执行，即它阻塞了下一条语句的执行.
• 非阻塞分配是并行执行的，即它们不会阻塞紧随其后的语句的执行.

假设a = 2和b = 3然后是非阻塞分配:

Suppose a = 2 and b = 3 then non-blocking assignments:

a <= 4;
b <= a; 

得出a = 4和b = 2-赋值前的值

results in a = 4 and b = 2 - value of a before assignment

但是

a = 4;
b = a;

阻塞分配完成后，将得到a = 4和b = 4-a的值.

Will result in a=4 and b=4 - value of a after the blocking assignment completes.

与组合逻辑相结合的变量(组合到寄存器(锁存器或触发器))取决于Always块的敏感度列表.它不取决于使用阻塞分配还是非阻塞分配.

A variable getting synthesized to a register (latch or flip-flop) vs. combinatorial logic depends on the sensitivity list of the always block. It does not depend on use of blocking or non-blocking assignment.

例如:

always @(*) begin
  if (enable)
     q = d;
end

这将导致D锁存，因为在enable == 0时未指定对q的赋值，因此需要记住是最后一次赋值.

This will result in a D-latch since assignment to q is not specified for when enable==0 so it needs to remember is last assignment.

而

always @(*) begin
  if (enable)
    q = d;
  else
    q = f;
end

这将导致多路复用(组合逻辑)，因为在两种启用情况下都指定了对q的分配，因此q不需要记住任何内容.

This will result in a mux (combinatorial logic) since assignment to q is specified for both cases of enable and so q need not remember anything.

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